Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2488	1			T1	1		T3	2		T21	2
non_zero_bins[1]	1836	1			T3	11		T21	1		T13	5
zero	8612	1			T1	2		T3	1		T8	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	495	1			T23	1		T34	7		T35	7
uni	3313	1			T3	1		T21	3		T37	2
gen	4225	1			T3	10		T8	2		T19	1
res	820	1			T1	2		T3	2		T13	2
ins	4083	1			T1	1		T3	1		T8	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8399

1

T3

12

T8

1

T9

1

mubi_true

4537

1

T1

3

T3

2

T8

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

17

1

T261

1

T277

1

T278

1

pass

12919

1

T1

3

T3

14

T8

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	129	1			T34	3		T35	3		T36	2
upd	non_zero_bins[0]	pass	mubi_true	113	1			T23	1		T101	1		T59	2
upd	non_zero_bins[1]	pass	mubi_false	77	1			T35	1		T36	1		T60	1
upd	non_zero_bins[1]	pass	mubi_true	76	1			T34	1		T35	2		T36	1
upd	zero	pass	mubi_false	49	1			T34	1		T35	1		T59	1
upd	zero	pass	mubi_true	51	1			T34	2		T36	1		T59	1
uni	zero	pass	mubi_false	2454	1			T3	1		T21	2		T37	1
uni	zero	pass	mubi_true	859	1			T21	1		T37	1		T62	1
gen	non_zero_bins[0]	pass	mubi_false	459	1			T3	1		T23	2		T18	4
gen	non_zero_bins[0]	pass	mubi_true	488	1			T21	1		T13	1		T34	5
gen	non_zero_bins[1]	pass	mubi_false	353	1			T3	9		T13	3		T23	1
gen	non_zero_bins[1]	pass	mubi_true	378	1			T63	3		T34	3		T35	4
gen	zero	fail	mubi_false	17	1			T261	1		T277	1		T278	1
gen	zero	pass	mubi_false	1742	1			T20	1		T4	1		T22	1
gen	zero	pass	mubi_true	788	1			T8	2		T19	1		T9	2
res	non_zero_bins[0]	pass	mubi_false	161	1			T18	2		T63	2		T34	3
res	non_zero_bins[0]	pass	mubi_true	181	1			T23	1		T34	3		T38	2
res	non_zero_bins[1]	pass	mubi_false	140	1			T13	2		T34	1		T35	1
res	non_zero_bins[1]	pass	mubi_true	148	1			T3	2		T23	1		T18	1
res	zero	pass	mubi_false	104	1			T23	1		T36	1		T59	2
res	zero	pass	mubi_true	86	1			T1	2		T34	1		T35	2
ins	non_zero_bins[0]	pass	mubi_false	491	1			T3	1		T23	1		T34	8
ins	non_zero_bins[0]	pass	mubi_true	466	1			T1	1		T21	1		T37	1
ins	non_zero_bins[1]	pass	mubi_false	357	1			T34	6		T35	6		T40	1
ins	non_zero_bins[1]	pass	mubi_true	307	1			T21	1		T23	4		T34	1
ins	zero	pass	mubi_false	1866	1			T8	1		T9	1		T4	1
ins	zero	pass	mubi_true	596	1			T8	1		T19	2		T9	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded