Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T22,T49
1	1	Covered	T19,T20,T21

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T9,T5
1	1	Covered	T1,T3,T8

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T20
1	0	Covered	T2,T5,T28

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T8,T9,T20
1	Covered	T2,T5,T28

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T8,T9,T20
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T5,T28

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T3,T13
AutoCaptGenCnt	143	Covered	T1,T3,T13
AutoCaptReseedCnt	141	Covered	T1,T3,T13
AutoDispatch	125	Covered	T1,T3,T13
AutoFirstAckWait	119	Covered	T1,T3,T8
AutoLoadIns	69	Covered	T1,T3,T8
AutoSendGenCmd	150	Covered	T1,T3,T13
AutoSendReseedCmd	162	Covered	T1,T3,T13
BootDone	98	Covered	T19,T20,T21
BootGenAckWait	90	Covered	T19,T20,T21
BootInsAckWait	80	Covered	T19,T20,T21
BootLoadGen	85	Covered	T19,T20,T21
BootLoadIns	65	Covered	T19,T20,T21
BootLoadUni	102	Covered	T20,T21,T64
BootPulse	94	Covered	T19,T20,T21
BootUniAckWait	107	Covered	T20,T21,T64
Error	188	Covered	T2,T5,T28
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T8,T9,T20
SWPortMode	74	Covered	T2,T3,T8

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T3,T13
AutoAckWait->Error	188	Covered	T117
AutoAckWait->Idle	211	Covered	T1,T18,T40
AutoAckWait->RejectCsrngEntropy	188	Covered	T69,T74,T88
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T3,T13
AutoCaptGenCnt->Error	188	Covered	T54,T118
AutoCaptGenCnt->Idle	211	Covered	T77,T90,T119
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T120,T121,T122
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T3,T13
AutoCaptReseedCnt->Error	188	Covered	T123,T124
AutoCaptReseedCnt->Idle	211	Covered	T87,T125,T126
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T89,T71,T127
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T3,T13
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T3,T13
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T3,T13,T63
AutoDispatch->RejectCsrngEntropy	188	Covered	T66,T128,T129
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T3,T13
AutoFirstAckWait->Error	188	Covered	T6,T55,T130
AutoFirstAckWait->Idle	211	Covered	T102,T131,T132
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T8,T133,T86
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T3,T8
AutoLoadIns->Error	188	Covered	T134,T135,T136
AutoLoadIns->Idle	211	Covered	T1,T5,T6
AutoLoadIns->RejectCsrngEntropy	188	Covered	T9,T137,T138
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T3,T13
AutoSendGenCmd->Error	188	Covered	T5,T109,T139
AutoSendGenCmd->Idle	211	Covered	T140,T141,T142
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T41,T45,T143
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T3,T13
AutoSendReseedCmd->Error	188	Covered	T144,T145,T146
AutoSendReseedCmd->Idle	211	Covered	T147,T148,T149
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T150,T151,T110
BootDone->BootLoadUni	102	Covered	T20,T21,T64
BootDone->Error	188	Covered	T152,T153,T154
BootDone->Idle	211	Covered	T49,T68,T155
BootDone->RejectCsrngEntropy	188	Covered	T106,T156,T157
BootGenAckWait->BootPulse	94	Covered	T19,T20,T21
BootGenAckWait->Error	188	Covered	T158,T159,T160
BootGenAckWait->Idle	211	Covered	T161,T162,T163
BootGenAckWait->RejectCsrngEntropy	188	Covered	T64,T104,T164
BootInsAckWait->BootLoadGen	85	Covered	T19,T20,T21
BootInsAckWait->Error	188	Covered	T68,T53,T165
BootInsAckWait->Idle	211	Covered	T19,T22,T67
BootInsAckWait->RejectCsrngEntropy	188	Covered	T20,T47,T82
BootLoadGen->BootGenAckWait	90	Covered	T19,T20,T21
BootLoadGen->Error	188	Covered	T166
BootLoadGen->Idle	211	Covered	T167,T168,T169
BootLoadGen->RejectCsrngEntropy	188	Covered	T170,T171,T172
BootLoadIns->BootInsAckWait	80	Covered	T19,T20,T21
BootLoadIns->Error	188	Covered	T14,T173,T174
BootLoadIns->Idle	211	Covered	T175,T176,T177
BootLoadIns->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootLoadUni->BootUniAckWait	107	Covered	T20,T21,T64
BootLoadUni->Error	188	Covered	T181,T182,T183
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T116,T184,T185
BootPulse->BootDone	98	Covered	T19,T20,T21
BootPulse->Error	188	Covered	T186
BootPulse->Idle	211	Covered	T187,T188,T189
BootPulse->RejectCsrngEntropy	188	Covered	T91,T190,T191
BootUniAckWait->Error	188	Covered	T192,T193,T194
BootUniAckWait->Idle	112	Covered	T20,T21,T64
BootUniAckWait->RejectCsrngEntropy	188	Covered	T70,T195,T196
Idle->AutoLoadIns	69	Covered	T1,T3,T8
Idle->BootLoadIns	65	Covered	T19,T20,T21
Idle->Error	188	Covered	T2,T15,T16
Idle->RejectCsrngEntropy	188	Covered	T8,T20,T66
Idle->SWPortMode	74	Covered	T2,T3,T8
RejectCsrngEntropy->Error	188	Covered	T197,T198,T199
RejectCsrngEntropy->Idle	211	Covered	T8,T9,T20
SWPortMode->Error	188	Covered	T2,T28,T15
SWPortMode->Idle	211	Covered	T2,T8,T9
SWPortMode->RejectCsrngEntropy	188	Covered	T9,T69,T64

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T21,T64
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T19,T20,T22
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T64
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T200,T48
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T20,T21,T64
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T3,T8
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T3,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T3,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T13,T63
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T3,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T3,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T8
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T20
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T67,T7

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T2,T5,T28
1	0	1	-	Not Covered
1	0	0	-	Covered	T8,T9,T20
0	-	-	1	Covered	T1,T8,T19
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	195977335	139465	0	0
FpvSecCmErrorStEscalate_A	195977335	140630	0	0
u_state_regs_A	195941285	195749700	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	139465	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	220	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	349	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	140630	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	221	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	350	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195941285	195749700	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	741	578	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0