Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T19
DataWait	75	Covered	T1,T3,T19
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T19
DataWait->AckPls	80	Covered	T1,T3,T19
DataWait->Disabled	107	Covered	T19,T77,T90
DataWait->Error	99	Covered	T5,T202,T203
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T19
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T19
Idle	-	1	0	-	Covered	T1,T3,T19
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T19
DataWait	-	-	-	0	Covered	T1,T3,T19
AckPls	-	-	-	-	Covered	T1,T3,T19
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T28,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1371841345	986655	0	0
FpvSecCmErrorStEscalate_A	1371841345	994810	0	0
u_state_regs_A	1371805295	1370464200	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371841345	986655	0	0
T2	328293	129171	0	0
T3	22442	0	0	0
T4	5285	0	0	0
T5	0	1274	0	0
T6	0	7650	0	0
T7	0	1890	0	0
T8	19103	0	0	0
T9	19271	0	0	0
T14	0	3164	0	0
T15	0	95823	0	0
T19	4347	0	0	0
T20	16030	0	0	0
T21	11753	0	0	0
T22	8659	0	0	0
T28	0	1616	0	0
T37	17213	0	0	0
T51	0	7861	0	0
T67	0	2793	0	0
T68	0	1756	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371841345	994810	0	0
T2	328293	130991	0	0
T3	22442	0	0	0
T4	5285	0	0	0
T5	0	1281	0	0
T6	0	7657	0	0
T7	0	1897	0	0
T8	19103	0	0	0
T9	19271	0	0	0
T14	0	3171	0	0
T15	0	97643	0	0
T19	4347	0	0	0
T20	16030	0	0	0
T21	11753	0	0	0
T22	8659	0	0	0
T28	0	1623	0	0
T37	17213	0	0	0
T51	0	7868	0	0
T67	0	2800	0	0
T68	0	1763	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1371805295	1370464200	0	0
T1	20398	19999	0	0
T2	328293	180649	0	0
T3	22442	22064	0	0
T4	5271	4130	0	0
T8	19103	18599	0	0
T9	19271	18683	0	0
T19	4347	3724	0	0
T20	16030	15407	0	0
T21	11753	11186	0	0
T22	8659	8162	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T9,T21
DataWait	75	Covered	T3,T9,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T9,T21
DataWait->AckPls	80	Covered	T3,T9,T21
DataWait->Disabled	107	Covered	T205,T206,T142
DataWait->Error	99	Covered	T5,T202,T203
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T9,T21
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T67,T7

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T9,T21
Idle	-	1	0	-	Covered	T3,T9,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T9,T21
DataWait	-	-	-	0	Covered	T3,T9,T21
AckPls	-	-	-	-	Covered	T3,T9,T21
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T28,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	138765	0	0
FpvSecCmErrorStEscalate_A	195977335	139930	0	0
u_state_regs_A	195941285	195749700	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	138765	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1050	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	188	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	208	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	139930	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1051	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	189	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	209	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195941285	195749700	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	741	578	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T21,T13
DataWait	75	Covered	T19,T21,T13
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T21,T13
DataWait->AckPls	80	Covered	T19,T21,T13
DataWait->Disabled	107	Covered	T19,T90,T140
DataWait->Error	99	Covered	T53,T152,T181
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T19,T21,T13
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T19,T21,T13
Idle	-	1	0	-	Covered	T19,T21,T13
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T19,T21,T13
DataWait	-	-	-	0	Covered	T19,T21,T13
AckPls	-	-	-	-	Covered	T19,T21,T13
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T20,T21
DataWait	75	Covered	T1,T20,T21
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T20,T21
DataWait->AckPls	80	Covered	T1,T20,T21
DataWait->Disabled	107	Covered	T207,T163,T208
DataWait->Error	99	Covered	T209,T182,T210
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T20,T21
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T20,T21
Idle	-	1	0	-	Covered	T1,T20,T21
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T20,T21
DataWait	-	-	-	0	Covered	T1,T20,T21
AckPls	-	-	-	-	Covered	T1,T20,T21
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T37,T38,T39
DataWait	75	Covered	T37,T38,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T37,T38,T39
DataWait->AckPls	80	Covered	T37,T38,T39
DataWait->Disabled	107	Covered	T77,T167,T168
DataWait->Error	99	Covered	T211,T212,T158
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T37,T38,T39
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T37,T38,T39
Idle	-	1	0	-	Covered	T37,T38,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T37,T38,T39
DataWait	-	-	-	0	Covered	T37,T38,T39
AckPls	-	-	-	-	Covered	T37,T38,T39
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T21,T38
DataWait	75	Covered	T8,T21,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T21,T38
DataWait->AckPls	80	Covered	T8,T21,T38
DataWait->Disabled	107	Covered	T141,T162,T213
DataWait->Error	99	Covered	T214,T197,T215
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T21,T38
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T21,T38
Idle	-	1	0	-	Covered	T8,T21,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T21,T38
DataWait	-	-	-	0	Covered	T8,T21,T38
AckPls	-	-	-	-	Covered	T8,T21,T38
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T4,T21,T22
DataWait	75	Covered	T4,T21,T22
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T4,T21,T22
DataWait->AckPls	80	Covered	T4,T21,T22
DataWait->Disabled	107	Covered	T22,T216,T217
DataWait->Error	99	Covered	T218
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T21,T22
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T4,T21,T22
Idle	-	1	0	-	Covered	T4,T21,T22
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T4,T21,T22
DataWait	-	-	-	0	Covered	T21,T22,T49
AckPls	-	-	-	-	Covered	T4,T21,T22
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T19

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T21,T18,T40
DataWait	75	Covered	T21,T18,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T28
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T21,T18,T40
DataWait->AckPls	80	Covered	T21,T18,T40
DataWait->Disabled	107	Covered	T219,T220,T119
DataWait->Error	99	Covered	T7,T221,T198
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T2,T15,T16
EndPointClear->Disabled	107	Covered	T23,T17,T204
EndPointClear->Error	99	Covered	T2,T14,T15
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T21,T18,T40
Idle->Disabled	107	Covered	T1,T2,T8
Idle->Error	99	Covered	T2,T5,T28

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T21,T18,T40
Idle	-	1	0	-	Covered	T21,T18,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T21,T18,T40
DataWait	-	-	-	0	Covered	T21,T40,T47
AckPls	-	-	-	-	Covered	T21,T18,T40
Error	-	-	-	-	Covered	T2,T5,T28
default	-	-	-	-	Covered	T2,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T28
0	1	Covered	T1,T8,T19
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	195977335	141315	0	0
FpvSecCmErrorStEscalate_A	195977335	142480	0	0
u_state_regs_A	195977335	195785750	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	141315	0	0
T2	46899	18453	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	182	0	0
T6	0	1100	0	0
T7	0	270	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	452	0	0
T15	0	13689	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	238	0	0
T37	2459	0	0	0
T51	0	1123	0	0
T67	0	399	0	0
T68	0	258	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	142480	0	0
T2	46899	18713	0	0
T3	3206	0	0	0
T4	755	0	0	0
T5	0	183	0	0
T6	0	1101	0	0
T7	0	271	0	0
T8	2729	0	0	0
T9	2753	0	0	0
T14	0	453	0	0
T15	0	13949	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T28	0	239	0	0
T37	2459	0	0	0
T51	0	1124	0	0
T67	0	400	0	0
T68	0	259	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0