Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T92,T93
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T32,T33
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	391178868	1059277	0	0
DepthKnown_A	391954670	391571500	0	0
RvalidKnown_A	391954670	391571500	0	0
WreadyKnown_A	391954670	391571500	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	391513794	1142234	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391178868	1059277	0	0
T1	5828	2892	0	0
T2	1514	0	0	0
T3	6412	1995	0	0
T4	464	0	0	0
T5	0	111	0	0
T6	0	47	0	0
T8	5458	633	0	0
T9	5506	572	0	0
T13	0	4843	0	0
T18	0	2574	0	0
T19	1242	0	0	0
T20	4580	0	0	0
T21	3358	0	0	0
T22	2474	0	0	0
T63	0	2498	0	0
T69	0	555	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391954670	391571500	0	0
T1	5828	5714	0	0
T2	93798	51614	0	0
T3	6412	6304	0	0
T4	1510	1184	0	0
T8	5458	5314	0	0
T9	5506	5338	0	0
T19	1242	1064	0	0
T20	4580	4402	0	0
T21	3358	3196	0	0
T22	2474	2332	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391954670	391571500	0	0
T1	5828	5714	0	0
T2	93798	51614	0	0
T3	6412	6304	0	0
T4	1510	1184	0	0
T8	5458	5314	0	0
T9	5506	5338	0	0
T19	1242	1064	0	0
T20	4580	4402	0	0
T21	3358	3196	0	0
T22	2474	2332	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391954670	391571500	0	0
T1	5828	5714	0	0
T2	93798	51614	0	0
T3	6412	6304	0	0
T4	1510	1184	0	0
T8	5458	5314	0	0
T9	5506	5338	0	0
T19	1242	1064	0	0
T20	4580	4402	0	0
T21	3358	3196	0	0
T22	2474	2332	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	391513794	1142234	0	0
T1	5828	2892	0	0
T2	1514	0	0	0
T3	6412	1995	0	0
T4	1510	7	0	0
T5	0	464	0	0
T6	0	745	0	0
T8	5458	633	0	0
T9	5506	572	0	0
T13	0	4843	0	0
T18	0	2574	0	0
T19	1242	0	0	0
T20	4580	0	0	0
T21	3358	0	0	0
T22	2474	0	0	0
T63	0	2498	0	0
T69	0	555	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T94
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T93,T95
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T96,T97
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195589434	524481	0	0
DepthKnown_A	195977335	195785750	0	0
RvalidKnown_A	195977335	195785750	0	0
WreadyKnown_A	195977335	195785750	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195756897	565822	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195589434	524481	0	0
T1	2914	1426	0	0
T2	757	0	0	0
T3	3206	978	0	0
T4	232	0	0	0
T5	0	55	0	0
T6	0	13	0	0
T8	2729	322	0	0
T9	2753	218	0	0
T13	0	2410	0	0
T18	0	1231	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T63	0	1215	0	0
T69	0	279	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195756897	565822	0	0
T1	2914	1426	0	0
T2	757	0	0	0
T3	3206	978	0	0
T4	755	0	0	0
T5	0	280	0	0
T6	0	745	0	0
T8	2729	322	0	0
T9	2753	218	0	0
T13	0	2410	0	0
T18	0	1231	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T63	0	1215	0	0
T69	0	279	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T92
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T32,T33
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195589434	534796	0	0
DepthKnown_A	195977335	195785750	0	0
RvalidKnown_A	195977335	195785750	0	0
WreadyKnown_A	195977335	195785750	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195756897	576412	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195589434	534796	0	0
T1	2914	1466	0	0
T2	757	0	0	0
T3	3206	1017	0	0
T4	232	0	0	0
T5	0	56	0	0
T6	0	34	0	0
T8	2729	311	0	0
T9	2753	354	0	0
T13	0	2433	0	0
T18	0	1343	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T63	0	1283	0	0
T69	0	276	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195977335	195785750	0	0
T1	2914	2857	0	0
T2	46899	25807	0	0
T3	3206	3152	0	0
T4	755	592	0	0
T8	2729	2657	0	0
T9	2753	2669	0	0
T19	621	532	0	0
T20	2290	2201	0	0
T21	1679	1598	0	0
T22	1237	1166	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195756897	576412	0	0
T1	2914	1466	0	0
T2	757	0	0	0
T3	3206	1017	0	0
T4	755	7	0	0
T5	0	184	0	0
T8	2729	311	0	0
T9	2753	354	0	0
T13	0	2433	0	0
T18	0	1343	0	0
T19	621	0	0	0
T20	2290	0	0	0
T21	1679	0	0	0
T22	1237	0	0	0
T63	0	1283	0	0
T69	0	276	0	0