Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	664496	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5421616

1

T1

4

T2

36

T3

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1599812	1			T1	1		T2	52		T3	354
values[0x0]	2071529	1			T1	1		T2	22		T3	21
values[0x1]	2414771	1			T1	4		T2	11		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	325942	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5760170

1

T1

4

T2

53

T3

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23573	1			T4	3		T11	2		T12	1
valid_sources[0x01]	23366	1			T4	4		T43	1		T6	3
valid_sources[0x02]	23752	1			T4	6		T6	2		T61	2
valid_sources[0x03]	23217	1			T4	1		T31	2		T43	1
valid_sources[0x04]	24518	1			T4	4		T11	1		T43	1
valid_sources[0x05]	24957	1			T4	1		T11	3		T42	2
valid_sources[0x06]	23382	1			T4	3		T6	3		T238	1
valid_sources[0x07]	22810	1			T4	1		T6	9		T238	1
valid_sources[0x08]	23080	1			T4	1		T13	16		T12	2
valid_sources[0x09]	22891	1			T4	3		T13	4		T43	2
valid_sources[0x0a]	23442	1			T2	1		T4	2		T11	1
valid_sources[0x0b]	24420	1			T4	1		T12	1		T6	2
valid_sources[0x0c]	25350	1			T11	3		T6	2		T238	1
valid_sources[0x0d]	24832	1			T4	3		T42	1		T43	2
valid_sources[0x0e]	25529	1			T4	5		T26	3		T6	1
valid_sources[0x0f]	24411	1			T4	2		T6	2		T8	1
valid_sources[0x10]	24366	1			T12	1		T6	3		T238	1
valid_sources[0x11]	23042	1			T2	2		T4	4		T27	97
valid_sources[0x12]	23207	1			T2	10		T4	1		T11	1
valid_sources[0x13]	25185	1			T4	2		T12	1		T42	19
valid_sources[0x14]	22927	1			T4	3		T12	1		T43	3
valid_sources[0x15]	24808	1			T4	1		T42	1		T43	1
valid_sources[0x16]	23425	1			T4	2		T31	1		T42	1
valid_sources[0x17]	24698	1			T4	5		T13	14		T12	1
valid_sources[0x18]	23340	1			T4	1		T6	1		T47	1
valid_sources[0x19]	23794	1			T4	4		T11	1		T12	1
valid_sources[0x1a]	24491	1			T4	3		T31	1		T6	2
valid_sources[0x1b]	24237	1			T4	3		T6	3		T61	3
valid_sources[0x1c]	24026	1			T4	3		T13	1		T12	1
valid_sources[0x1d]	23318	1			T4	2		T42	2		T6	2
valid_sources[0x1e]	24364	1			T4	6		T26	3		T6	2
valid_sources[0x1f]	24456	1			T4	4		T31	1		T6	4
valid_sources[0x20]	23580	1			T4	1		T11	1		T76	10
valid_sources[0x21]	23942	1			T4	3		T6	3		T239	2
valid_sources[0x22]	22157	1			T4	2		T11	1		T31	2
valid_sources[0x23]	22788	1			T4	5		T42	1		T6	4
valid_sources[0x24]	23556	1			T4	1		T6	2		T60	1
valid_sources[0x25]	22812	1			T4	5		T42	1		T6	6
valid_sources[0x26]	25303	1			T4	6		T11	1		T31	1
valid_sources[0x27]	24737	1			T4	1		T12	1		T43	1
valid_sources[0x28]	22267	1			T4	1		T11	1		T6	3
valid_sources[0x29]	23140	1			T4	5		T12	1		T6	3
valid_sources[0x2a]	22024	1			T4	1		T12	1		T61	1
valid_sources[0x2b]	24285	1			T4	7		T13	3		T6	6
valid_sources[0x2c]	23425	1			T4	5		T12	1		T31	2
valid_sources[0x2d]	23560	1			T3	396		T4	3		T6	7
valid_sources[0x2e]	21643	1			T4	1		T12	1		T6	1
valid_sources[0x2f]	24130	1			T4	2		T6	1		T47	1
valid_sources[0x30]	24149	1			T4	4		T31	1		T43	1
valid_sources[0x31]	26299	1			T4	3		T31	1		T42	1
valid_sources[0x32]	23205	1			T4	2		T11	2		T13	4
valid_sources[0x33]	23948	1			T4	1		T11	1		T76	1
valid_sources[0x34]	24121	1			T2	3		T4	1		T26	3
valid_sources[0x35]	23694	1			T11	1		T12	1		T16	3
valid_sources[0x36]	23737	1			T4	4		T6	4		T62	1
valid_sources[0x37]	25913	1			T4	3		T6	5		T61	3
valid_sources[0x38]	23086	1			T4	1		T12	1		T6	2
valid_sources[0x39]	23892	1			T4	1		T11	1		T42	6
valid_sources[0x3a]	26599	1			T2	1		T4	4		T31	2
valid_sources[0x3b]	24662	1			T4	1		T11	1		T31	1
valid_sources[0x3c]	24044	1			T4	5		T11	1		T31	1
valid_sources[0x3d]	22129	1			T4	1		T31	1		T42	1
valid_sources[0x3e]	24045	1			T4	1		T6	3		T8	1
valid_sources[0x3f]	23838	1			T4	5		T13	3		T12	1
valid_sources[0x40]	23980	1			T4	5		T26	1		T6	3
valid_sources[0x41]	23086	1			T4	5		T13	2		T31	1
valid_sources[0x42]	22906	1			T4	6		T11	1		T13	4
valid_sources[0x43]	23067	1			T2	4		T4	2		T26	1
valid_sources[0x44]	24583	1			T4	1		T43	1		T6	5
valid_sources[0x45]	25147	1			T4	2		T11	2		T26	1
valid_sources[0x46]	23172	1			T4	1		T31	1		T76	2
valid_sources[0x47]	24091	1			T4	1		T42	1		T6	5
valid_sources[0x48]	24577	1			T4	2		T43	1		T6	2
valid_sources[0x49]	23484	1			T4	1		T26	3		T12	2
valid_sources[0x4a]	23243	1			T4	1		T42	6		T6	2
valid_sources[0x4b]	23985	1			T2	9		T26	1		T12	1
valid_sources[0x4c]	22707	1			T4	4		T42	3		T6	1
valid_sources[0x4d]	23779	1			T4	1		T6	7		T47	1
valid_sources[0x4e]	23673	1			T4	4		T6	2		T77	1
valid_sources[0x4f]	24854	1			T4	3		T12	1		T31	1
valid_sources[0x50]	22394	1			T4	2		T31	1		T6	2
valid_sources[0x51]	25111	1			T4	4		T76	4		T43	1
valid_sources[0x52]	25230	1			T4	3		T31	1		T6	1
valid_sources[0x53]	24901	1			T4	2		T26	1		T43	2
valid_sources[0x54]	23125	1			T26	2		T31	1		T76	2
valid_sources[0x55]	22855	1			T4	1		T43	2		T6	3
valid_sources[0x56]	26520	1			T76	3		T6	2		T60	2
valid_sources[0x57]	23252	1			T4	3		T12	1		T6	2
valid_sources[0x58]	23910	1			T4	3		T31	1		T77	2
valid_sources[0x59]	24844	1			T4	2		T26	2		T13	3
valid_sources[0x5a]	23812	1			T4	3		T6	2		T238	1
valid_sources[0x5b]	24505	1			T4	5		T6	2		T62	2
valid_sources[0x5c]	25251	1			T4	4		T6	3		T77	50
valid_sources[0x5d]	23499	1			T4	3		T13	7		T12	2
valid_sources[0x5e]	23455	1			T6	4		T47	3		T60	1
valid_sources[0x5f]	24953	1			T4	3		T12	1		T6	1
valid_sources[0x60]	22086	1			T4	2		T26	1		T13	3
valid_sources[0x61]	22604	1			T4	2		T11	1		T13	5
valid_sources[0x62]	24245	1			T4	2		T11	1		T6	1
valid_sources[0x63]	25302	1			T2	3		T6	6		T8	3
valid_sources[0x64]	25596	1			T4	1		T12	2		T6	3
valid_sources[0x65]	23046	1			T4	4		T13	4		T31	1
valid_sources[0x66]	23565	1			T4	2		T26	2		T76	3
valid_sources[0x67]	23005	1			T4	2		T43	1		T6	2
valid_sources[0x68]	24558	1			T4	4		T76	5		T43	1
valid_sources[0x69]	22392	1			T4	3		T43	2		T6	4
valid_sources[0x6a]	24615	1			T42	2		T6	6		T8	1
valid_sources[0x6b]	23546	1			T4	1		T26	1		T6	4
valid_sources[0x6c]	22723	1			T4	4		T11	1		T26	1
valid_sources[0x6d]	23090	1			T4	6		T42	1		T43	1
valid_sources[0x6e]	25288	1			T4	5		T11	1		T26	1
valid_sources[0x6f]	23669	1			T4	1		T6	1		T60	2
valid_sources[0x70]	24829	1			T4	3		T11	7		T26	1
valid_sources[0x71]	24582	1			T4	5		T42	1		T6	8
valid_sources[0x72]	23773	1			T4	4		T42	1		T6	1
valid_sources[0x73]	22748	1			T4	5		T12	1		T31	1
valid_sources[0x74]	24330	1			T4	1		T6	2		T60	1
valid_sources[0x75]	23030	1			T1	6		T4	4		T13	9
valid_sources[0x76]	22528	1			T12	2		T31	1		T6	3
valid_sources[0x77]	22883	1			T4	1		T31	1		T6	5
valid_sources[0x78]	21736	1			T6	4		T60	1		T238	1
valid_sources[0x79]	22646	1			T4	1		T6	1		T60	1
valid_sources[0x7a]	23605	1			T4	2		T43	1		T6	4
valid_sources[0x7b]	22635	1			T4	4		T43	1		T6	2
valid_sources[0x7c]	25197	1			T4	2		T11	1		T43	1
valid_sources[0x7d]	23370	1			T4	1		T12	4		T6	3
valid_sources[0x7e]	23352	1			T4	1		T11	15		T13	3
valid_sources[0x7f]	21807	1			T4	4		T11	1		T31	1
valid_sources[0x80]	23355	1			T4	5		T12	1		T31	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1366429

1

T1

1

T2

6

T3

8

values[0x0]

all_enables

biggest_size

2028286

1

T1

1

T2

20

T3

18

values[0x1]

all_enables

biggest_size

2026901

1

T1

2

T2

10

T3

20