Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2607	1			T2	1		T4	2		T10	3
non_zero_bins[1]	1791	1			T2	2		T3	3		T4	5
zero	8712	1			T1	4		T2	4		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	511	1			T4	1		T27	1		T6	2
uni	3459	1			T2	2		T3	1		T4	9
gen	4149	1			T1	2		T2	2		T3	1
res	817	1			T2	1		T3	1		T4	1
ins	4174	1			T1	2		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8667

1

T1

4

T2

4

T3

3

mubi_true

4443

1

T2

3

T3

1

T4

5

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

18

1

T11

1

T47

1

T271

1

pass

13092

1

T1

4

T2

7

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	107	1			T41	1		T74	2		T46	1
upd	non_zero_bins[0]	pass	mubi_true	126	1			T27	1		T239	1		T39	1
upd	non_zero_bins[1]	pass	mubi_false	93	1			T4	1		T6	1		T61	1
upd	non_zero_bins[1]	pass	mubi_true	89	1			T48	1		T49	1		T39	2
upd	zero	pass	mubi_false	44	1			T6	1		T44	1		T74	1
upd	zero	pass	mubi_true	52	1			T49	1		T226	1		T41	1
uni	zero	pass	mubi_false	2574	1			T2	2		T3	1		T4	8
uni	zero	pass	mubi_true	885	1			T4	1		T75	1		T6	5
gen	non_zero_bins[0]	pass	mubi_false	507	1			T4	2		T27	1		T13	5
gen	non_zero_bins[0]	pass	mubi_true	461	1			T12	3		T6	1		T60	1
gen	non_zero_bins[1]	pass	mubi_false	352	1			T48	1		T49	1		T39	1
gen	non_zero_bins[1]	pass	mubi_true	316	1			T2	1		T3	1		T4	1
gen	zero	fail	mubi_false	16	1			T11	1		T47	1		T271	1
gen	zero	pass	mubi_false	1794	1			T1	2		T2	1		T4	5
gen	zero	pass	mubi_true	703	1			T11	2		T26	3		T13	1
res	non_zero_bins[0]	pass	mubi_false	178	1			T10	2		T6	2		T238	1
res	non_zero_bins[0]	pass	mubi_true	196	1			T2	1		T13	2		T6	2
res	non_zero_bins[1]	pass	mubi_false	122	1			T3	1		T39	1		T41	1
res	non_zero_bins[1]	pass	mubi_true	113	1			T4	1		T6	1		T41	1
res	zero	fail	mubi_false	2	1			T152	1		T153	1		-	-
res	zero	pass	mubi_false	118	1			T12	6		T76	1		T41	2
res	zero	pass	mubi_true	88	1			T39	1		T40	1		T41	1
ins	non_zero_bins[0]	pass	mubi_false	515	1			T12	1		T6	4		T239	1
ins	non_zero_bins[0]	pass	mubi_true	517	1			T10	1		T75	2		T6	1
ins	non_zero_bins[1]	pass	mubi_false	363	1			T3	1		T4	1		T10	1
ins	non_zero_bins[1]	pass	mubi_true	343	1			T2	1		T4	1		T13	1
ins	zero	pass	mubi_false	1882	1			T1	2		T2	1		T4	6
ins	zero	pass	mubi_true	554	1			T4	1		T11	1		T26	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded