Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T4
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T1,T184,T185
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T4
DataWait->AckPls	80	Covered	T2,T3,T4
DataWait->Disabled	107	Covered	T93,T82,T171
DataWait->Error	99	Covered	T17,T79,T9
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T4
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T4
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T2,T3,T4
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T7,T102,T103

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1544228336	1116571	0	0
FpvSecCmErrorStEscalate_A	1544228336	1125643	0	0
u_state_regs_A	1544191571	1542781610	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544228336	1116571	0	0
T7	11361	6320	0	0
T8	9520	3024	0	0
T9	0	7770	0	0
T16	15463	7910	0	0
T17	0	7714	0	0
T47	18655	0	0	0
T50	0	7504	0	0
T51	0	8372	0	0
T57	9933	0	0	0
T58	21231	0	0	0
T59	11865	0	0	0
T60	29729	0	0	0
T61	32781	0	0	0
T62	13083	0	0	0
T78	0	2310	0	0
T79	0	2597	0	0
T102	0	8133	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544228336	1125643	0	0
T7	11361	6327	0	0
T8	9520	3031	0	0
T9	0	7777	0	0
T16	15463	7917	0	0
T17	0	7721	0	0
T47	18655	0	0	0
T50	0	7511	0	0
T51	0	8379	0	0
T57	9933	0	0	0
T58	21231	0	0	0
T59	11865	0	0	0
T60	29729	0	0	0
T61	32781	0	0	0
T62	13083	0	0	0
T78	0	2317	0	0
T79	0	2604	0	0
T102	0	8140	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1544191571	1542781610	0	0
T1	5642	5054	0	0
T2	28469	27874	0	0
T3	25305	24738	0	0
T4	161889	155309	0	0
T5	5640	4506	0	0
T10	28497	27881	0	0
T11	20741	20104	0	0
T13	24605	24003	0	0
T26	15127	14497	0	0
T27	14959	14525	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T12,T31
DataWait	75	Covered	T3,T12,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T12,T31
DataWait->AckPls	80	Covered	T3,T12,T31
DataWait->Disabled	107	Covered	T82
DataWait->Error	99	Covered	T132,T195,T190
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T12,T31
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T12,T31
Idle	-	1	0	-	Covered	T3,T12,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T12,T31
DataWait	-	-	-	0	Covered	T3,T12,T31
AckPls	-	-	-	-	Covered	T3,T12,T31
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T42,T43
DataWait	75	Covered	T13,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T42,T43
DataWait->AckPls	80	Covered	T13,T42,T43
DataWait->Disabled	107	Covered	T196,T197,T198
DataWait->Error	99	Covered	T56,T199,T136
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T13,T42,T43
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T13,T42,T43
Idle	-	1	0	-	Covered	T13,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T13,T42,T43
DataWait	-	-	-	0	Covered	T13,T42,T43
AckPls	-	-	-	-	Covered	T13,T42,T43
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T26,T13
DataWait	75	Covered	T3,T26,T13
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T26,T13
DataWait->AckPls	80	Covered	T3,T26,T13
DataWait->Disabled	107	Covered	T144,T145,T200
DataWait->Error	99	Covered	T55,T201,T202
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T26,T13
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T26,T13
Idle	-	1	0	-	Covered	T3,T26,T13
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T26,T13
DataWait	-	-	-	0	Covered	T3,T26,T13
AckPls	-	-	-	-	Covered	T3,T26,T13
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T10,T5
DataWait	75	Covered	T3,T10,T5
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T10,T5
DataWait->AckPls	80	Covered	T3,T10,T5
DataWait->Disabled	107	Covered	T93,T203
DataWait->Error	99	Covered	T170,T204
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T10,T5
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T10,T5
Idle	-	1	0	-	Covered	T3,T10,T5
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T10,T5
DataWait	-	-	-	0	Covered	T3,T10,T13
AckPls	-	-	-	-	Covered	T3,T10,T5
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T4
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T205,T206
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T4
DataWait->AckPls	80	Covered	T2,T3,T4
DataWait->Disabled	107	Covered	T173,T143,T207
DataWait->Error	99	Covered	T79,T9,T51
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T50,T194,T208
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T4
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T4
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T2,T3,T4
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T7,T102,T103

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	158053	0	0
FpvSecCmErrorStEscalate_A	220604048	159349	0	0
u_state_regs_A	220567283	220365860	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	158053	0	0
T7	1623	860	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1119	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159349	0	0
T7	1623	861	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1120	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220567283	220365860	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	756	594	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T11
DataWait	75	Covered	T2,T3,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T184,T209
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T11
DataWait->AckPls	80	Covered	T2,T3,T11
DataWait->Disabled	107	Covered	T210,T211
DataWait->Error	99	Covered	T17,T118,T142
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T11
Idle->Disabled	107	Covered	T1,T4,T10
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T11
Idle	-	1	0	-	Covered	T2,T3,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T11
DataWait	-	-	-	0	Covered	T2,T3,T11
AckPls	-	-	-	-	Covered	T2,T3,T11
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T10,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T3,T48
DataWait	75	Covered	T1,T3,T48
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T7,T16,T8
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T1,T185
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T3,T48
DataWait->AckPls	80	Covered	T1,T3,T48
DataWait->Disabled	107	Covered	T171,T122,T212
DataWait->Error	99	Covered	T54,T161,T69
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T6,T193,T87
EndPointClear->Error	99	Covered	T7,T50,T194
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T48
Idle->Disabled	107	Covered	T4,T10,T11
Idle->Error	99	Covered	T16,T8,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T48
Idle	-	1	0	-	Covered	T1,T3,T48
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T48
DataWait	-	-	-	0	Covered	T1,T3,T48
AckPls	-	-	-	-	Covered	T1,T3,T48
Error	-	-	-	-	Covered	T7,T16,T8
default	-	-	-	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T16,T8
0	1	Covered	T1,T10,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	220604048	159753	0	0
FpvSecCmErrorStEscalate_A	220604048	161049	0	0
u_state_regs_A	220604048	220402625	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	159753	0	0
T7	1623	910	0	0
T8	1360	432	0	0
T9	0	1110	0	0
T16	2209	1130	0	0
T17	0	1102	0	0
T47	2665	0	0	0
T50	0	1072	0	0
T51	0	1196	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	330	0	0
T79	0	371	0	0
T102	0	1169	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	161049	0	0
T7	1623	911	0	0
T8	1360	433	0	0
T9	0	1111	0	0
T16	2209	1131	0	0
T17	0	1103	0	0
T47	2665	0	0	0
T50	0	1073	0	0
T51	0	1197	0	0
T57	1419	0	0	0
T58	3033	0	0	0
T59	1695	0	0	0
T60	4247	0	0	0
T61	4683	0	0	0
T62	1869	0	0	0
T78	0	331	0	0
T79	0	372	0	0
T102	0	1170	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0