Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T35,T32
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T37,T38
1	0	1	Covered	T10,T11,T5
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	440378086	1032607	0	0
DepthKnown_A	441208096	440805250	0	0
RvalidKnown_A	441208096	440805250	0	0
WreadyKnown_A	441208096	440805250	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	440741766	1127888	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	440378086	1032607	0	0
T5	546	0	0	0
T7	0	57	0	0
T10	8142	5527	0	0
T11	5926	1184	0	0
T12	5816	3033	0	0
T13	7030	3657	0	0
T26	4322	0	0	0
T27	4274	0	0	0
T31	5080	442	0	0
T42	0	345	0	0
T43	0	553	0	0
T75	8510	0	0	0
T76	4520	343	0	0
T77	0	238	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441208096	440805250	0	0
T1	1612	1444	0	0
T2	8134	7964	0	0
T3	7230	7068	0	0
T4	46254	44374	0	0
T5	1628	1304	0	0
T10	8142	7966	0	0
T11	5926	5744	0	0
T13	7030	6858	0	0
T26	4322	4142	0	0
T27	4274	4150	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441208096	440805250	0	0
T1	1612	1444	0	0
T2	8134	7964	0	0
T3	7230	7068	0	0
T4	46254	44374	0	0
T5	1628	1304	0	0
T10	8142	7966	0	0
T11	5926	5744	0	0
T13	7030	6858	0	0
T26	4322	4142	0	0
T27	4274	4150	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441208096	440805250	0	0
T1	1612	1444	0	0
T2	8134	7964	0	0
T3	7230	7068	0	0
T4	46254	44374	0	0
T5	1628	1304	0	0
T10	8142	7966	0	0
T11	5926	5744	0	0
T13	7030	6858	0	0
T26	4322	4142	0	0
T27	4274	4150	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	440741766	1127888	0	0
T5	1628	19	0	0
T7	0	560	0	0
T10	8142	5527	0	0
T11	5926	1184	0	0
T12	5816	3033	0	0
T13	7030	3657	0	0
T26	4322	0	0	0
T27	4274	0	0	0
T31	5080	442	0	0
T42	0	345	0	0
T43	0	553	0	0
T75	8510	0	0	0
T76	4520	343	0	0
T77	0	238	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T21,T32
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T13

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T34,T98
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T13

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T99,T100
1	0	1	Covered	T10,T11,T13
1	1	0	Not Covered
1	1	1	Covered	T10,T13,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220189043	510518	0	0
DepthKnown_A	220604048	220402625	0	0
RvalidKnown_A	220604048	220402625	0	0
WreadyKnown_A	220604048	220402625	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220370883	557937	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220189043	510518	0	0
T5	273	0	0	0
T7	0	27	0	0
T10	4071	2729	0	0
T11	2963	584	0	0
T12	2908	1451	0	0
T13	3515	1782	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T31	2540	197	0	0
T42	0	166	0	0
T43	0	272	0	0
T75	4255	0	0	0
T76	2260	95	0	0
T77	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220370883	557937	0	0
T5	814	0	0	0
T7	0	560	0	0
T10	4071	2729	0	0
T11	2963	584	0	0
T12	2908	1451	0	0
T13	3515	1782	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T31	2540	197	0	0
T42	0	166	0	0
T43	0	272	0	0
T75	4255	0	0	0
T76	2260	95	0	0
T77	0	99	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T11,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T35
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T37,T38,T101
1	0	1	Covered	T10,T11,T5
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	220189043	522089	0	0
DepthKnown_A	220604048	220402625	0	0
RvalidKnown_A	220604048	220402625	0	0
WreadyKnown_A	220604048	220402625	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	220370883	569951	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220189043	522089	0	0
T5	273	0	0	0
T7	0	30	0	0
T10	4071	2798	0	0
T11	2963	600	0	0
T12	2908	1582	0	0
T13	3515	1875	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T31	2540	245	0	0
T42	0	179	0	0
T43	0	281	0	0
T75	4255	0	0	0
T76	2260	248	0	0
T77	0	139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220604048	220402625	0	0
T1	806	722	0	0
T2	4067	3982	0	0
T3	3615	3534	0	0
T4	23127	22187	0	0
T5	814	652	0	0
T10	4071	3983	0	0
T11	2963	2872	0	0
T13	3515	3429	0	0
T26	2161	2071	0	0
T27	2137	2075	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	220370883	569951	0	0
T5	814	19	0	0
T10	4071	2798	0	0
T11	2963	600	0	0
T12	2908	1582	0	0
T13	3515	1875	0	0
T26	2161	0	0	0
T27	2137	0	0	0
T31	2540	245	0	0
T42	0	179	0	0
T43	0	281	0	0
T75	4255	0	0	0
T76	2260	248	0	0
T77	0	139	0	0