Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	721103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5830723

1

T1

6

T2

44

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1732118	1			T1	13		T2	33		T3	44
values[0x0]	2228243	1			T1	5		T2	17		T3	4
values[0x1]	2591465	1			T1	5		T2	29		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	355617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6196209

1

T1

12

T2

54

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26640	1			T11	1		T4	1		T20	3
valid_sources[0x01]	25402	1			T10	1		T23	1		T4	7
valid_sources[0x02]	23969	1			T11	1		T4	5		T20	1
valid_sources[0x03]	25174	1			T10	1		T20	1		T39	404
valid_sources[0x04]	26810	1			T10	3		T31	2		T4	3
valid_sources[0x05]	26172	1			T11	1		T4	2		T39	390
valid_sources[0x06]	25193	1			T10	1		T23	1		T11	1
valid_sources[0x07]	26359	1			T10	3		T11	2		T4	3
valid_sources[0x08]	26776	1			T11	1		T4	2		T29	2
valid_sources[0x09]	26139	1			T11	1		T4	7		T39	396
valid_sources[0x0a]	25070	1			T3	2		T11	1		T4	6
valid_sources[0x0b]	25366	1			T23	1		T4	2		T20	2
valid_sources[0x0c]	25398	1			T10	1		T23	1		T4	2
valid_sources[0x0d]	25185	1			T3	1		T9	2		T11	1
valid_sources[0x0e]	27642	1			T8	5		T9	3		T11	1
valid_sources[0x0f]	27302	1			T11	4		T4	3		T39	395
valid_sources[0x10]	24921	1			T10	1		T4	7		T55	20
valid_sources[0x11]	26203	1			T11	1		T4	3		T39	426
valid_sources[0x12]	23949	1			T23	2		T4	3		T20	1
valid_sources[0x13]	24444	1			T11	1		T31	1		T4	4
valid_sources[0x14]	25290	1			T11	1		T4	3		T32	6
valid_sources[0x15]	26276	1			T11	2		T4	4		T32	1
valid_sources[0x16]	27270	1			T3	1		T8	1		T10	2
valid_sources[0x17]	24876	1			T9	3		T10	2		T4	4
valid_sources[0x18]	24251	1			T3	1		T4	2		T39	409
valid_sources[0x19]	26464	1			T2	1		T4	4		T39	426
valid_sources[0x1a]	24984	1			T9	1		T10	2		T4	9
valid_sources[0x1b]	27065	1			T2	7		T22	6		T4	3
valid_sources[0x1c]	25418	1			T9	2		T11	1		T31	1
valid_sources[0x1d]	25743	1			T22	1		T11	2		T4	1
valid_sources[0x1e]	25596	1			T23	1		T11	1		T4	1
valid_sources[0x1f]	25454	1			T2	3		T9	1		T23	1
valid_sources[0x20]	25208	1			T11	1		T4	8		T39	412
valid_sources[0x21]	25604	1			T3	1		T4	4		T55	13
valid_sources[0x22]	25075	1			T9	1		T10	2		T11	2
valid_sources[0x23]	24620	1			T9	1		T11	1		T4	7
valid_sources[0x24]	26186	1			T2	1		T11	1		T4	4
valid_sources[0x25]	26775	1			T28	5		T4	1		T20	1
valid_sources[0x26]	24948	1			T11	2		T4	10		T32	1
valid_sources[0x27]	26637	1			T11	1		T4	4		T32	1
valid_sources[0x28]	24624	1			T10	1		T11	2		T4	5
valid_sources[0x29]	24814	1			T8	2		T9	1		T11	1
valid_sources[0x2a]	25623	1			T8	2		T9	1		T4	2
valid_sources[0x2b]	25188	1			T1	1		T3	1		T4	4
valid_sources[0x2c]	25347	1			T11	2		T4	1		T32	2
valid_sources[0x2d]	26479	1			T3	2		T8	5		T22	7
valid_sources[0x2e]	24665	1			T1	1		T9	1		T11	1
valid_sources[0x2f]	27157	1			T23	1		T11	2		T4	2
valid_sources[0x30]	25740	1			T3	1		T4	5		T32	2
valid_sources[0x31]	26734	1			T11	2		T4	3		T39	409
valid_sources[0x32]	26037	1			T22	1		T4	3		T39	391
valid_sources[0x33]	24932	1			T3	2		T10	2		T4	3
valid_sources[0x34]	27400	1			T9	1		T10	3		T11	2
valid_sources[0x35]	26548	1			T9	1		T11	1		T4	2
valid_sources[0x36]	25891	1			T9	2		T11	1		T31	2
valid_sources[0x37]	24841	1			T2	2		T10	1		T4	5
valid_sources[0x38]	25447	1			T1	1		T8	6		T9	1
valid_sources[0x39]	24842	1			T11	4		T4	5		T39	387
valid_sources[0x3a]	24708	1			T3	2		T8	1		T11	2
valid_sources[0x3b]	24911	1			T1	1		T10	2		T11	2
valid_sources[0x3c]	26030	1			T11	1		T4	4		T20	2
valid_sources[0x3d]	25077	1			T11	2		T4	2		T20	2
valid_sources[0x3e]	26668	1			T3	1		T4	4		T20	1
valid_sources[0x3f]	26614	1			T4	2		T39	360		T40	603
valid_sources[0x40]	24516	1			T9	1		T23	1		T11	1
valid_sources[0x41]	24090	1			T11	1		T4	2		T39	422
valid_sources[0x42]	26267	1			T10	1		T11	2		T4	4
valid_sources[0x43]	25351	1			T11	3		T4	3		T39	353
valid_sources[0x44]	25361	1			T10	3		T11	2		T4	11
valid_sources[0x45]	25189	1			T3	2		T4	2		T20	2
valid_sources[0x46]	25885	1			T31	1		T4	6		T39	384
valid_sources[0x47]	26233	1			T9	1		T10	1		T4	4
valid_sources[0x48]	26848	1			T22	2		T4	3		T20	1
valid_sources[0x49]	24081	1			T8	1		T9	1		T11	2
valid_sources[0x4a]	25384	1			T11	2		T4	4		T39	367
valid_sources[0x4b]	25692	1			T9	1		T31	4		T4	3
valid_sources[0x4c]	25794	1			T11	1		T4	1		T39	412
valid_sources[0x4d]	24981	1			T10	1		T11	1		T4	4
valid_sources[0x4e]	24841	1			T8	1		T4	6		T32	1
valid_sources[0x4f]	25501	1			T4	2		T55	33		T20	1
valid_sources[0x50]	25049	1			T8	4		T11	3		T4	2
valid_sources[0x51]	25223	1			T4	5		T39	473		T40	646
valid_sources[0x52]	25533	1			T2	1		T11	2		T31	2
valid_sources[0x53]	25146	1			T3	2		T10	1		T4	2
valid_sources[0x54]	25123	1			T4	7		T39	409		T40	628
valid_sources[0x55]	25640	1			T10	1		T11	1		T4	1
valid_sources[0x56]	25454	1			T1	1		T11	1		T4	3
valid_sources[0x57]	23531	1			T8	1		T4	7		T32	4
valid_sources[0x58]	27470	1			T11	2		T31	3		T4	2
valid_sources[0x59]	25365	1			T1	1		T10	1		T11	1
valid_sources[0x5a]	25347	1			T3	1		T11	1		T4	4
valid_sources[0x5b]	25892	1			T8	2		T11	3		T4	7
valid_sources[0x5c]	25403	1			T3	1		T23	1		T11	2
valid_sources[0x5d]	24761	1			T1	1		T9	1		T11	1
valid_sources[0x5e]	27512	1			T9	1		T11	2		T4	10
valid_sources[0x5f]	25647	1			T23	1		T4	3		T39	393
valid_sources[0x60]	25381	1			T11	1		T4	3		T39	384
valid_sources[0x61]	25616	1			T4	2		T20	1		T39	367
valid_sources[0x62]	24852	1			T2	1		T4	4		T32	1
valid_sources[0x63]	25922	1			T11	2		T4	5		T39	381
valid_sources[0x64]	25701	1			T1	1		T10	2		T11	3
valid_sources[0x65]	25623	1			T9	1		T11	2		T31	1
valid_sources[0x66]	25872	1			T9	1		T11	1		T4	3
valid_sources[0x67]	24692	1			T4	3		T20	1		T39	413
valid_sources[0x68]	25423	1			T10	2		T11	1		T4	2
valid_sources[0x69]	26290	1			T10	2		T11	1		T4	4
valid_sources[0x6a]	26203	1			T4	2		T29	1		T39	361
valid_sources[0x6b]	24352	1			T9	1		T4	4		T39	412
valid_sources[0x6c]	25512	1			T3	1		T11	1		T4	3
valid_sources[0x6d]	24909	1			T4	5		T55	29		T20	1
valid_sources[0x6e]	25011	1			T9	1		T11	1		T4	4
valid_sources[0x6f]	25874	1			T11	3		T4	3		T39	436
valid_sources[0x70]	24602	1			T11	1		T31	2		T4	6
valid_sources[0x71]	24978	1			T11	1		T4	4		T20	2
valid_sources[0x72]	26185	1			T11	2		T4	7		T39	415
valid_sources[0x73]	24556	1			T1	1		T9	1		T31	4
valid_sources[0x74]	23933	1			T11	1		T4	5		T29	2
valid_sources[0x75]	24757	1			T3	3		T11	2		T4	2
valid_sources[0x76]	25914	1			T11	1		T4	1		T39	393
valid_sources[0x77]	27208	1			T3	3		T9	1		T10	2
valid_sources[0x78]	24753	1			T22	2		T4	6		T55	52
valid_sources[0x79]	26323	1			T1	1		T10	1		T4	1
valid_sources[0x7a]	25565	1			T9	2		T10	2		T11	1
valid_sources[0x7b]	26120	1			T11	1		T4	5		T32	1
valid_sources[0x7c]	25067	1			T11	1		T4	4		T55	24
valid_sources[0x7d]	24578	1			T31	3		T4	3		T20	1
valid_sources[0x7e]	24382	1			T4	4		T32	1		T39	391
valid_sources[0x7f]	25614	1			T9	1		T11	1		T31	3
valid_sources[0x80]	25503	1			T4	1		T39	370		T40	659

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1468666

1

T1

3

T2

9

T3

5

values[0x0]

all_enables

biggest_size

2182328

1

T1

2

T2

14

T3

1

values[0x1]

all_enables

biggest_size

2179729

1

T1

1

T2

21

T3

2