Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2907	1			T8	4		T9	1		T11	4
non_zero_bins[1]	2046	1			T9	7		T10	1		T11	5
zero	9635	1			T1	2		T2	5		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	574	1			T4	2		T77	1		T30	1
uni	3881	1			T8	1		T11	1		T24	2
gen	4589	1			T1	1		T2	3		T3	1
res	886	1			T8	2		T9	4		T10	1
ins	4658	1			T1	1		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9630

1

T1

2

T2

2

T3

2

mubi_true

4958

1

T2

3

T8

2

T9

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

18

1

T32

1

T54

1

T123

1

pass

14570

1

T1

2

T2

5

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	135	1			T4	1		T77	1		T39	2
upd	non_zero_bins[0]	pass	mubi_true	135	1			T4	1		T39	1		T40	4
upd	non_zero_bins[1]	pass	mubi_false	102	1			T39	4		T40	1		T41	3
upd	non_zero_bins[1]	pass	mubi_true	87	1			T30	1		T40	2		T41	1
upd	zero	pass	mubi_false	59	1			T39	1		T40	2		T42	1
upd	zero	pass	mubi_true	56	1			T41	1		T228	1		T229	1
uni	zero	pass	mubi_false	2882	1			T8	1		T11	1		T24	1
uni	zero	pass	mubi_true	999	1			T24	1		T4	2		T55	4
gen	non_zero_bins[0]	pass	mubi_false	541	1			T8	4		T30	1		T39	4
gen	non_zero_bins[0]	pass	mubi_true	538	1			T11	1		T4	2		T77	1
gen	non_zero_bins[1]	pass	mubi_false	375	1			T9	3		T11	5		T4	1
gen	non_zero_bins[1]	pass	mubi_true	392	1			T24	1		T4	3		T55	2
gen	zero	fail	mubi_false	15	1			T32	1		T54	1		T123	1
gen	zero	pass	mubi_false	1991	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	737	1			T2	2		T31	2		T28	1
res	non_zero_bins[0]	pass	mubi_false	219	1			T4	1		T55	1		T39	2
res	non_zero_bins[0]	pass	mubi_true	210	1			T11	2		T20	3		T40	4
res	non_zero_bins[1]	pass	mubi_false	146	1			T9	4		T4	1		T55	1
res	non_zero_bins[1]	pass	mubi_true	133	1			T55	1		T39	1		T40	3
res	zero	fail	mubi_false	3	1			T169	1		T170	1		T284	1
res	zero	pass	mubi_false	93	1			T10	1		T39	1		T49	1
res	zero	pass	mubi_true	82	1			T8	2		T55	1		T39	2
ins	non_zero_bins[0]	pass	mubi_false	549	1			T11	1		T4	3		T77	1
ins	non_zero_bins[0]	pass	mubi_true	580	1			T9	1		T24	1		T4	4
ins	non_zero_bins[1]	pass	mubi_false	414	1			T4	2		T55	4		T39	9
ins	non_zero_bins[1]	pass	mubi_true	397	1			T10	1		T4	1		T20	1
ins	zero	pass	mubi_false	2106	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	612	1			T2	1		T24	1		T31	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded