Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=20,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	20	20

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	4	4

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	3860	3860	0	0
OutputsKnown_A	904800880	904013132	0	0
gen_no_flops.OutputDelay_A	904800880	904013132	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3860	3860	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0
T24	4	4	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904800880	904013132	0	0
T1	3440	2852	0	0
T2	10552	10352	0	0
T3	1792	1032	0	0
T8	6992	6776	0	0
T9	11572	11252	0	0
T10	8036	7716	0	0
T11	13664	13288	0	0
T22	6380	6140	0	0
T23	5048	4744	0	0
T24	4940	4552	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	904800880	904013132	0	0
T1	3440	2852	0	0
T2	10552	10352	0	0
T3	1792	1032	0	0
T8	6992	6776	0	0
T9	11572	11252	0	0
T10	8036	7716	0	0
T11	13664	13288	0	0
T22	6380	6140	0	0
T23	5048	4744	0	0
T24	4940	4552	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	20	20

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	226200220	226003283	0	0
gen_no_flops.OutputDelay_A	226200220	226003283	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	4	4

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	226200220	226003283	0	0
gen_no_flops.OutputDelay_A	226200220	226003283	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	226200220	226003283	0	0
gen_no_flops.OutputDelay_A	226200220	226003283	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	226200220	226003283	0	0
gen_no_flops.OutputDelay_A	226200220	226003283	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0