Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T8
DataWait	75	Covered	T1,T2,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T90,T92
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T8
DataWait->AckPls	80	Covered	T1,T2,T8
DataWait->Disabled	107	Covered	T129,T87,T179
DataWait->Error	99	Covered	T15,T16,T111
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T8
Idle	-	1	0	-	Covered	T1,T2,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T8
DataWait	-	-	-	0	Covered	T2,T8,T11
AckPls	-	-	-	-	Covered	T1,T2,T8
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T78,T79,T110

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1583401540	1110610	0	0
FpvSecCmErrorStEscalate_A	1583401540	1119703	0	0
u_state_regs_A	1583367316	1581988757	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583401540	1110610	0	0
T14	15575	7973	0	0
T15	0	1771	0	0
T16	0	7959	0	0
T20	13776	0	0	0
T29	6153	3136	0	0
T30	22659	0	0	0
T39	2906050	0	0	0
T40	3347141	0	0	0
T51	0	5858	0	0
T54	17199	0	0	0
T55	126910	0	0	0
T62	18172	0	0	0
T63	22484	0	0	0
T78	0	2743	0	0
T79	0	7720	0	0
T110	0	4080	0	0
T111	0	2520	0	0
T112	0	4438	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583401540	1119703	0	0
T14	15575	7980	0	0
T15	0	1778	0	0
T16	0	7966	0	0
T20	13776	0	0	0
T29	6153	3143	0	0
T30	22659	0	0	0
T39	2906050	0	0	0
T40	3347141	0	0	0
T51	0	5865	0	0
T54	17199	0	0	0
T55	126910	0	0	0
T62	18172	0	0	0
T63	22484	0	0	0
T78	0	2750	0	0
T79	0	7727	0	0
T110	0	4087	0	0
T111	0	2527	0	0
T112	0	4445	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583367316	1581988757	0	0
T1	5945	4916	0	0
T2	18466	18116	0	0
T3	3122	1792	0	0
T8	12236	11858	0	0
T9	20251	19691	0	0
T10	14063	13503	0	0
T11	23912	23254	0	0
T22	11165	10745	0	0
T23	8834	8302	0	0
T24	8645	7966	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T11,T31
DataWait	75	Covered	T8,T11,T31
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T11,T31
DataWait->AckPls	80	Covered	T8,T11,T31
DataWait->Disabled	107	Covered	T129,T179,T204
DataWait->Error	99	Covered	T111,T112,T57
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T56,T58,T205
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T11,T31
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T11,T31
Idle	-	1	0	-	Covered	T8,T11,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T11,T31
DataWait	-	-	-	0	Covered	T8,T11,T31
AckPls	-	-	-	-	Covered	T8,T11,T31
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T78,T79,T110

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	157030	0	0
FpvSecCmErrorStEscalate_A	226200220	158329	0	0
u_state_regs_A	226165996	225969059	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	157030	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	794	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	349	0	0
T79	0	1060	0	0
T110	0	540	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158329	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	795	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	350	0	0
T79	0	1061	0	0
T110	0	541	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226165996	225969059	0	0
T1	785	638	0	0
T2	2638	2588	0	0
T3	434	244	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T8
DataWait	75	Covered	T1,T2,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T8
DataWait->AckPls	80	Covered	T1,T2,T8
DataWait->Disabled	107	Covered	T206,T207,T208
DataWait->Error	99	Covered	T209,T178,T133
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T8
Idle	-	1	0	-	Covered	T1,T2,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T8
DataWait	-	-	-	0	Covered	T8,T24,T42
AckPls	-	-	-	-	Covered	T1,T2,T8
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T24,T32
DataWait	75	Covered	T2,T24,T32
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T24,T32
DataWait->AckPls	80	Covered	T2,T24,T32
DataWait->Disabled	107	Covered	T87,T210,T211
DataWait->Error	99	Covered	T15,T16,T5
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T24,T32
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T78

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T24,T32
Idle	-	1	0	-	Covered	T2,T24,T32
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T24,T32
DataWait	-	-	-	0	Covered	T2,T24,T32
AckPls	-	-	-	-	Covered	T2,T24,T32
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T14,T20
DataWait	75	Covered	T8,T14,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T14,T20
DataWait->AckPls	80	Covered	T8,T14,T20
DataWait->Disabled	107	Covered	T180,T166,T134
DataWait->Error	99	Covered	T171,T212,T213
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T14,T20
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T14,T20
Idle	-	1	0	-	Covered	T8,T14,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T14,T20
DataWait	-	-	-	0	Covered	T8,T20,T42
AckPls	-	-	-	-	Covered	T8,T14,T20
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T9,T24
DataWait	75	Covered	T8,T9,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T9,T24
DataWait->AckPls	80	Covered	T8,T9,T24
DataWait->Disabled	107	Covered	T214,T70,T215
DataWait->Error	99	Covered	T132,T216,T202
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T9,T24
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T9,T24
Idle	-	1	0	-	Covered	T8,T9,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T9,T24
DataWait	-	-	-	0	Covered	T8,T9,T24
AckPls	-	-	-	-	Covered	T8,T9,T24
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T8,T10
DataWait	75	Covered	T3,T8,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T8,T10
DataWait->AckPls	80	Covered	T3,T8,T10
DataWait->Disabled	107	Covered	T100,T74,T217
DataWait->Error	99	Covered	T193,T173,T218
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T8,T10
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T8,T10
Idle	-	1	0	-	Covered	T3,T8,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T8,T10
DataWait	-	-	-	0	Covered	T8,T10,T42
AckPls	-	-	-	-	Covered	T3,T8,T10
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T42,T43
DataWait	75	Covered	T24,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T29,T14,T15
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T90,T92
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T42,T43
DataWait->AckPls	80	Covered	T24,T42,T43
DataWait->Disabled	107	Covered	T160,T219
DataWait->Error	99	Covered	T220,T197,T200
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T17,T18,T19
EndPointClear->Disabled	107	Covered	T9,T55,T115
EndPointClear->Error	99	Covered	T79,T110,T56
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T42,T43
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T29,T14,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T42,T43
Idle	-	1	0	-	Covered	T24,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T42,T43
DataWait	-	-	-	0	Covered	T24,T42,T43
AckPls	-	-	-	-	Covered	T24,T42,T43
Error	-	-	-	-	Covered	T29,T14,T15
default	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T14,T15
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

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Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	226200220	158930	0	0
FpvSecCmErrorStEscalate_A	226200220	160229	0	0
u_state_regs_A	226200220	226003283	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	158930	0	0
T14	2225	1139	0	0
T15	0	253	0	0
T16	0	1137	0	0
T20	1968	0	0	0
T29	879	448	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	844	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	399	0	0
T79	0	1110	0	0
T110	0	590	0	0
T111	0	360	0	0
T112	0	634	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	160229	0	0
T14	2225	1140	0	0
T15	0	254	0	0
T16	0	1138	0	0
T20	1968	0	0	0
T29	879	449	0	0
T30	3237	0	0	0
T39	415150	0	0	0
T40	478163	0	0	0
T51	0	845	0	0
T54	2457	0	0	0
T55	18130	0	0	0
T62	2596	0	0	0
T63	3212	0	0	0
T78	0	400	0	0
T79	0	1111	0	0
T110	0	591	0	0
T111	0	361	0	0
T112	0	635	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0