Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T102,T103
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T37,T38
1	0	1	Covered	T1,T2,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	451620774	629932	0	0
DepthKnown_A	452400440	452006566	0	0
RvalidKnown_A	452400440	452006566	0	0
WreadyKnown_A	452400440	452006566	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	451962090	707137	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451620774	629932	0	0
T2	5276	237	0	0
T3	424	0	0	0
T8	3496	990	0	0
T9	5786	2974	0	0
T10	4018	2832	0	0
T11	6832	2231	0	0
T20	0	1834	0	0
T22	3190	0	0	0
T23	2524	0	0	0
T24	2470	0	0	0
T31	3036	0	0	0
T32	0	683	0	0
T54	0	1023	0	0
T62	0	1152	0	0
T63	0	703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452400440	452006566	0	0
T1	1720	1426	0	0
T2	5276	5176	0	0
T3	896	516	0	0
T8	3496	3388	0	0
T9	5786	5626	0	0
T10	4018	3858	0	0
T11	6832	6644	0	0
T22	3190	3070	0	0
T23	2524	2372	0	0
T24	2470	2276	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452400440	452006566	0	0
T1	1720	1426	0	0
T2	5276	5176	0	0
T3	896	516	0	0
T8	3496	3388	0	0
T9	5786	5626	0	0
T10	4018	3858	0	0
T11	6832	6644	0	0
T22	3190	3070	0	0
T23	2524	2372	0	0
T24	2470	2276	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	452400440	452006566	0	0
T1	1720	1426	0	0
T2	5276	5176	0	0
T3	896	516	0	0
T8	3496	3388	0	0
T9	5786	5626	0	0
T10	4018	3858	0	0
T11	6832	6644	0	0
T22	3190	3070	0	0
T23	2524	2372	0	0
T24	2470	2276	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	451962090	707137	0	0
T1	860	37	0	0
T2	5276	237	0	0
T3	896	0	0	0
T8	3496	990	0	0
T9	5786	2974	0	0
T10	4018	2832	0	0
T11	6832	2231	0	0
T20	0	1834	0	0
T22	3190	0	0	0
T23	2524	0	0	0
T24	2470	0	0	0
T29	0	295	0	0
T31	1518	0	0	0
T32	0	683	0	0
T54	0	1023	0	0
T62	0	591	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T104,T105
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T106
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T37,T38,T107
1	0	1	Covered	T1,T2,T8
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	225810387	309201	0	0
DepthKnown_A	226200220	226003283	0	0
RvalidKnown_A	226200220	226003283	0	0
WreadyKnown_A	226200220	226003283	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	225981045	347680	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225810387	309201	0	0
T2	2638	80	0	0
T3	212	0	0	0
T8	1748	425	0	0
T9	2893	1460	0	0
T10	2009	1330	0	0
T11	3416	1106	0	0
T20	0	904	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T31	1518	0	0	0
T32	0	335	0	0
T54	0	478	0	0
T62	0	561	0	0
T63	0	324	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	225981045	347680	0	0
T1	860	37	0	0
T2	2638	80	0	0
T3	448	0	0	0
T8	1748	425	0	0
T9	2893	1460	0	0
T10	2009	1330	0	0
T11	3416	1106	0	0
T20	0	904	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	156	0	0
T32	0	335	0	0
T54	0	478	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T102,T103
1	1	0	Not Covered
1	1	1	Covered	T2,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T108,T109
1	0	1	Covered	T2,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	225810387	320731	0	0
DepthKnown_A	226200220	226003283	0	0
RvalidKnown_A	226200220	226003283	0	0
WreadyKnown_A	226200220	226003283	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	225981045	359457	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225810387	320731	0	0
T2	2638	157	0	0
T3	212	0	0	0
T8	1748	565	0	0
T9	2893	1514	0	0
T10	2009	1502	0	0
T11	3416	1125	0	0
T20	0	930	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T31	1518	0	0	0
T32	0	348	0	0
T54	0	545	0	0
T62	0	591	0	0
T63	0	379	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226200220	226003283	0	0
T1	860	713	0	0
T2	2638	2588	0	0
T3	448	258	0	0
T8	1748	1694	0	0
T9	2893	2813	0	0
T10	2009	1929	0	0
T11	3416	3322	0	0
T22	1595	1535	0	0
T23	1262	1186	0	0
T24	1235	1138	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	225981045	359457	0	0
T2	2638	157	0	0
T3	448	0	0	0
T8	1748	565	0	0
T9	2893	1514	0	0
T10	2009	1502	0	0
T11	3416	1125	0	0
T20	0	930	0	0
T22	1595	0	0	0
T23	1262	0	0	0
T24	1235	0	0	0
T29	0	139	0	0
T31	1518	0	0	0
T32	0	348	0	0
T54	0	545	0	0
T62	0	591	0	0