Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.62 98.25 93.91 97.07 91.86 96.37 99.77 92.08


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1019 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2918274869 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 22627938 ps
T1020 /workspace/coverage/cover_reg_top/9.edn_intr_test.994689150 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 22733310 ps
T263 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.198761966 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:45 PM PDT 24 16408917 ps
T1021 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.106525186 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:45 PM PDT 24 27859463 ps
T1022 /workspace/coverage/cover_reg_top/12.edn_intr_test.1612405471 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:54 PM PDT 24 25539815 ps
T275 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3417416432 Jun 24 05:43:56 PM PDT 24 Jun 24 05:43:59 PM PDT 24 30329479 ps
T1023 /workspace/coverage/cover_reg_top/11.edn_intr_test.2287969003 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 18210321 ps
T1024 /workspace/coverage/cover_reg_top/11.edn_tl_errors.941534775 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:49 PM PDT 24 203199515 ps
T1025 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.242839788 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:54 PM PDT 24 91960565 ps
T276 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2592137307 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:51 PM PDT 24 17219485 ps
T264 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2229743374 Jun 24 05:43:23 PM PDT 24 Jun 24 05:43:25 PM PDT 24 56410536 ps
T1026 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2121337030 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:51 PM PDT 24 122969249 ps
T277 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2589168448 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 15890388 ps
T265 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2858333782 Jun 24 05:43:39 PM PDT 24 Jun 24 05:43:41 PM PDT 24 71312427 ps
T1027 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1455637870 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:54 PM PDT 24 31544469 ps
T278 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2612074946 Jun 24 05:43:50 PM PDT 24 Jun 24 05:43:55 PM PDT 24 16301556 ps
T1028 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2233418202 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 84473604 ps
T1029 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2584778482 Jun 24 05:43:39 PM PDT 24 Jun 24 05:43:41 PM PDT 24 44462287 ps
T1030 /workspace/coverage/cover_reg_top/0.edn_intr_test.388389523 Jun 24 05:43:32 PM PDT 24 Jun 24 05:43:34 PM PDT 24 16143809 ps
T1031 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2412041586 Jun 24 05:43:33 PM PDT 24 Jun 24 05:43:35 PM PDT 24 100372585 ps
T1032 /workspace/coverage/cover_reg_top/3.edn_tl_errors.255185525 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:48 PM PDT 24 158339154 ps
T1033 /workspace/coverage/cover_reg_top/45.edn_intr_test.1108823454 Jun 24 05:44:00 PM PDT 24 Jun 24 05:44:02 PM PDT 24 29429093 ps
T1034 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.408789420 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:46 PM PDT 24 22774409 ps
T1035 /workspace/coverage/cover_reg_top/27.edn_intr_test.688856702 Jun 24 05:44:12 PM PDT 24 Jun 24 05:44:15 PM PDT 24 14342246 ps
T1036 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1610541595 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 167325425 ps
T300 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1367388085 Jun 24 05:43:36 PM PDT 24 Jun 24 05:43:39 PM PDT 24 90503473 ps
T279 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2992589166 Jun 24 05:43:33 PM PDT 24 Jun 24 05:43:36 PM PDT 24 63654489 ps
T1037 /workspace/coverage/cover_reg_top/25.edn_intr_test.1987752749 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 14510962 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1444685669 Jun 24 05:43:24 PM PDT 24 Jun 24 05:43:26 PM PDT 24 427895555 ps
T1039 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1289234036 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:47 PM PDT 24 20156125 ps
T280 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2109934039 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:49 PM PDT 24 33700405 ps
T266 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3957978777 Jun 24 05:43:33 PM PDT 24 Jun 24 05:43:36 PM PDT 24 32485689 ps
T1040 /workspace/coverage/cover_reg_top/2.edn_intr_test.904051897 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:49 PM PDT 24 16483580 ps
T1041 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2838617891 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 68451629 ps
T1042 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.946442521 Jun 24 05:43:34 PM PDT 24 Jun 24 05:43:35 PM PDT 24 16185805 ps
T1043 /workspace/coverage/cover_reg_top/29.edn_intr_test.1686874903 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 37423288 ps
T1044 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1021380454 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:46 PM PDT 24 323995949 ps
T1045 /workspace/coverage/cover_reg_top/1.edn_tl_errors.860307183 Jun 24 05:43:35 PM PDT 24 Jun 24 05:43:39 PM PDT 24 122916111 ps
T1046 /workspace/coverage/cover_reg_top/31.edn_intr_test.2857758626 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:49 PM PDT 24 17915879 ps
T1047 /workspace/coverage/cover_reg_top/40.edn_intr_test.545942069 Jun 24 05:44:00 PM PDT 24 Jun 24 05:44:03 PM PDT 24 12957767 ps
T1048 /workspace/coverage/cover_reg_top/43.edn_intr_test.3519537994 Jun 24 05:44:07 PM PDT 24 Jun 24 05:44:09 PM PDT 24 13691367 ps
T1049 /workspace/coverage/cover_reg_top/20.edn_intr_test.2404703321 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:46 PM PDT 24 14455430 ps
T1050 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2003866918 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:54 PM PDT 24 15509188 ps
T1051 /workspace/coverage/cover_reg_top/18.edn_intr_test.1072254519 Jun 24 05:43:51 PM PDT 24 Jun 24 05:43:56 PM PDT 24 32073128 ps
T1052 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1084462428 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:48 PM PDT 24 242300932 ps
T1053 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2584133819 Jun 24 05:43:35 PM PDT 24 Jun 24 05:43:39 PM PDT 24 133364513 ps
T1054 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2733568021 Jun 24 05:43:31 PM PDT 24 Jun 24 05:43:35 PM PDT 24 128121394 ps
T1055 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1625050880 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 77977268 ps
T281 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2595353655 Jun 24 05:43:55 PM PDT 24 Jun 24 05:43:59 PM PDT 24 23599088 ps
T1056 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.866164842 Jun 24 05:43:37 PM PDT 24 Jun 24 05:43:45 PM PDT 24 44912335 ps
T1057 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4110793925 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:07 PM PDT 24 229002726 ps
T1058 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1963385258 Jun 24 05:43:37 PM PDT 24 Jun 24 05:43:39 PM PDT 24 33651502 ps
T1059 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.319902121 Jun 24 05:43:41 PM PDT 24 Jun 24 05:43:42 PM PDT 24 48745467 ps
T1060 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.880389733 Jun 24 05:43:51 PM PDT 24 Jun 24 05:43:57 PM PDT 24 52827618 ps
T1061 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2070326280 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:53 PM PDT 24 152040651 ps
T1062 /workspace/coverage/cover_reg_top/13.edn_csr_rw.726994815 Jun 24 05:43:52 PM PDT 24 Jun 24 05:43:57 PM PDT 24 17848960 ps
T1063 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1589293265 Jun 24 05:43:38 PM PDT 24 Jun 24 05:43:40 PM PDT 24 50699409 ps
T1064 /workspace/coverage/cover_reg_top/44.edn_intr_test.4284506429 Jun 24 05:44:01 PM PDT 24 Jun 24 05:44:03 PM PDT 24 114106877 ps
T1065 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2627294690 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:45 PM PDT 24 31091323 ps
T1066 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3418832039 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:09 PM PDT 24 102472434 ps
T1067 /workspace/coverage/cover_reg_top/21.edn_intr_test.1464463823 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:54 PM PDT 24 11736477 ps
T1068 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3645084617 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:48 PM PDT 24 339856668 ps
T1069 /workspace/coverage/cover_reg_top/19.edn_intr_test.2229743756 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 23879555 ps
T1070 /workspace/coverage/cover_reg_top/18.edn_tl_errors.84041502 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:47 PM PDT 24 36176765 ps
T267 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2676248521 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 23983566 ps
T1071 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4016961004 Jun 24 05:43:34 PM PDT 24 Jun 24 05:43:37 PM PDT 24 40214764 ps
T1072 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2779932863 Jun 24 05:43:38 PM PDT 24 Jun 24 05:43:40 PM PDT 24 76687667 ps
T1073 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3632040076 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:48 PM PDT 24 55571188 ps
T1074 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.887011343 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:56 PM PDT 24 180592709 ps
T1075 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3207985940 Jun 24 05:43:51 PM PDT 24 Jun 24 05:43:56 PM PDT 24 65058803 ps
T1076 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.63999158 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 71163153 ps
T1077 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1236759683 Jun 24 05:43:31 PM PDT 24 Jun 24 05:43:32 PM PDT 24 89094542 ps
T1078 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3368468902 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:48 PM PDT 24 155588402 ps
T268 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1773994520 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 19853742 ps
T1079 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1581917504 Jun 24 05:43:42 PM PDT 24 Jun 24 05:43:44 PM PDT 24 18240993 ps
T1080 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3624527781 Jun 24 05:43:40 PM PDT 24 Jun 24 05:43:43 PM PDT 24 202761102 ps
T1081 /workspace/coverage/cover_reg_top/14.edn_csr_rw.702121265 Jun 24 05:43:54 PM PDT 24 Jun 24 05:43:58 PM PDT 24 15124624 ps
T1082 /workspace/coverage/cover_reg_top/23.edn_intr_test.3443146972 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 13109274 ps
T1083 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2194848267 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:53 PM PDT 24 70121900 ps
T1084 /workspace/coverage/cover_reg_top/13.edn_intr_test.1687036290 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:54 PM PDT 24 22675395 ps
T1085 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1099602524 Jun 24 05:43:25 PM PDT 24 Jun 24 05:43:27 PM PDT 24 47245067 ps
T1086 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1412018710 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:55 PM PDT 24 719601279 ps
T1087 /workspace/coverage/cover_reg_top/26.edn_intr_test.127142752 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:49 PM PDT 24 33539795 ps
T1088 /workspace/coverage/cover_reg_top/22.edn_intr_test.3558252671 Jun 24 05:43:50 PM PDT 24 Jun 24 05:43:56 PM PDT 24 18660003 ps
T1089 /workspace/coverage/cover_reg_top/7.edn_intr_test.505144466 Jun 24 05:43:41 PM PDT 24 Jun 24 05:43:43 PM PDT 24 17847207 ps
T269 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1402679035 Jun 24 05:44:24 PM PDT 24 Jun 24 05:44:25 PM PDT 24 21389191 ps
T1090 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3603545105 Jun 24 05:43:43 PM PDT 24 Jun 24 05:43:45 PM PDT 24 163841315 ps
T1091 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1497579347 Jun 24 05:43:44 PM PDT 24 Jun 24 05:43:46 PM PDT 24 28298440 ps
T1092 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2451046658 Jun 24 05:43:34 PM PDT 24 Jun 24 05:43:36 PM PDT 24 39418685 ps
T1093 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2131323307 Jun 24 05:44:06 PM PDT 24 Jun 24 05:44:09 PM PDT 24 37028039 ps
T1094 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.715028563 Jun 24 05:43:34 PM PDT 24 Jun 24 05:43:36 PM PDT 24 40531791 ps
T1095 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.231025511 Jun 24 05:43:55 PM PDT 24 Jun 24 05:43:59 PM PDT 24 108141118 ps
T1096 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2300196442 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 531390730 ps
T1097 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3802416371 Jun 24 05:43:50 PM PDT 24 Jun 24 05:43:56 PM PDT 24 30393144 ps
T1098 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2644271340 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:51 PM PDT 24 64987803 ps
T1099 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2061643717 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 62403279 ps
T1100 /workspace/coverage/cover_reg_top/15.edn_tl_errors.4100694626 Jun 24 05:43:42 PM PDT 24 Jun 24 05:43:46 PM PDT 24 75690442 ps
T1101 /workspace/coverage/cover_reg_top/42.edn_intr_test.2260415407 Jun 24 05:44:11 PM PDT 24 Jun 24 05:44:13 PM PDT 24 50095791 ps
T1102 /workspace/coverage/cover_reg_top/34.edn_intr_test.3332020472 Jun 24 05:44:13 PM PDT 24 Jun 24 05:44:16 PM PDT 24 22183986 ps
T1103 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2919723620 Jun 24 05:43:50 PM PDT 24 Jun 24 05:43:56 PM PDT 24 173267578 ps
T1104 /workspace/coverage/cover_reg_top/38.edn_intr_test.1710692472 Jun 24 05:43:51 PM PDT 24 Jun 24 05:43:56 PM PDT 24 18545852 ps
T270 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.120289441 Jun 24 05:43:40 PM PDT 24 Jun 24 05:43:42 PM PDT 24 15586771 ps
T1105 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3101583162 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:49 PM PDT 24 34083563 ps
T1106 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1277271213 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:53 PM PDT 24 15130686 ps
T1107 /workspace/coverage/cover_reg_top/17.edn_intr_test.2888029228 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:50 PM PDT 24 22684583 ps
T1108 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3016645615 Jun 24 05:43:55 PM PDT 24 Jun 24 05:43:59 PM PDT 24 20284851 ps
T271 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2206222552 Jun 24 05:43:34 PM PDT 24 Jun 24 05:43:36 PM PDT 24 41138338 ps
T1109 /workspace/coverage/cover_reg_top/39.edn_intr_test.3640071012 Jun 24 05:44:04 PM PDT 24 Jun 24 05:44:06 PM PDT 24 45355240 ps
T1110 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.941481645 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:54 PM PDT 24 111736477 ps
T1111 /workspace/coverage/cover_reg_top/1.edn_intr_test.892565424 Jun 24 05:43:27 PM PDT 24 Jun 24 05:43:28 PM PDT 24 33896268 ps
T1112 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2609662035 Jun 24 05:43:41 PM PDT 24 Jun 24 05:43:46 PM PDT 24 288036165 ps
T1113 /workspace/coverage/cover_reg_top/28.edn_intr_test.1745223765 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:48 PM PDT 24 34976085 ps
T1114 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1292482222 Jun 24 05:43:41 PM PDT 24 Jun 24 05:43:43 PM PDT 24 23450232 ps
T1115 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2588314843 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:19 PM PDT 24 156670506 ps
T1116 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2081634726 Jun 24 05:43:38 PM PDT 24 Jun 24 05:43:40 PM PDT 24 30271272 ps
T1117 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2671198957 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:50 PM PDT 24 97417181 ps
T1118 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3480644671 Jun 24 05:43:45 PM PDT 24 Jun 24 05:43:48 PM PDT 24 47038170 ps
T1119 /workspace/coverage/cover_reg_top/5.edn_tl_errors.523227945 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:56 PM PDT 24 917730279 ps
T1120 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.613430325 Jun 24 05:43:37 PM PDT 24 Jun 24 05:43:38 PM PDT 24 13734239 ps
T1121 /workspace/coverage/cover_reg_top/4.edn_csr_rw.4207214549 Jun 24 05:43:38 PM PDT 24 Jun 24 05:43:40 PM PDT 24 33687700 ps
T1122 /workspace/coverage/cover_reg_top/46.edn_intr_test.1941462022 Jun 24 05:44:15 PM PDT 24 Jun 24 05:44:18 PM PDT 24 18431300 ps
T1123 /workspace/coverage/cover_reg_top/33.edn_intr_test.2015895928 Jun 24 05:43:49 PM PDT 24 Jun 24 05:43:55 PM PDT 24 43652525 ps
T1124 /workspace/coverage/cover_reg_top/16.edn_intr_test.2745829472 Jun 24 05:43:47 PM PDT 24 Jun 24 05:43:52 PM PDT 24 14300942 ps
T1125 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4166087013 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:54 PM PDT 24 20775650 ps
T1126 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1004996403 Jun 24 05:43:38 PM PDT 24 Jun 24 05:43:40 PM PDT 24 59994789 ps
T1127 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3887577762 Jun 24 05:43:48 PM PDT 24 Jun 24 05:43:56 PM PDT 24 120917940 ps
T1128 /workspace/coverage/cover_reg_top/36.edn_intr_test.3822824560 Jun 24 05:43:46 PM PDT 24 Jun 24 05:43:50 PM PDT 24 28544141 ps
T1129 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1881467324 Jun 24 05:43:36 PM PDT 24 Jun 24 05:43:41 PM PDT 24 606036550 ps
T272 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3410673007 Jun 24 05:43:42 PM PDT 24 Jun 24 05:43:51 PM PDT 24 25162598 ps

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2402027500
Short name T24
Test name
Test status
Simulation time 135215865216 ps
CPU time 890.3 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:43:35 PM PDT 24
Peak memory 221816 kb
Host smart-2bc18d69-76af-4465-b3b6-a825d8a1847b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402027500 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2402027500
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/212.edn_genbits.2790787752
Short name T12
Test name
Test status
Simulation time 102393217 ps
CPU time 1.35 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 218944 kb
Host smart-a09a2842-a807-47d7-9c75-17b22c493347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790787752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2790787752
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_alert.3997516678
Short name T78
Test name
Test status
Simulation time 236579899 ps
CPU time 1.17 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 219968 kb
Host smart-4e5a8d2b-afee-4465-bc3f-67e5c472cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997516678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3997516678
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2234186345
Short name T19
Test name
Test status
Simulation time 660460455 ps
CPU time 10 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 234928 kb
Host smart-c1ff2b88-1c03-4dbc-99d4-916965ca52b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234186345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2234186345
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/105.edn_genbits.1449953476
Short name T40
Test name
Test status
Simulation time 92530694 ps
CPU time 1.33 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 218532 kb
Host smart-a3aa0751-2f1f-4c4f-b318-7f0069925636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449953476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1449953476
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_err.3848415476
Short name T7
Test name
Test status
Simulation time 24427858 ps
CPU time 1.23 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 219008 kb
Host smart-3696a150-8987-4b16-9bf7-a0b470385c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848415476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3848415476
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/40.edn_stress_all.403691592
Short name T115
Test name
Test status
Simulation time 1971487928 ps
CPU time 4.11 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:17 PM PDT 24
Peak memory 219672 kb
Host smart-04885fac-7bec-4efb-94d1-2947f58e2ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403691592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.403691592
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1214558537
Short name T15
Test name
Test status
Simulation time 50979600 ps
CPU time 1.15 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 216164 kb
Host smart-cbbb89a4-189e-4e36-b5b8-1b7ccd26bca9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214558537 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1214558537
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/157.edn_alert.3069485075
Short name T1
Test name
Test status
Simulation time 78653906 ps
CPU time 1.18 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:44 PM PDT 24
Peak memory 218388 kb
Host smart-5e7b8083-65a7-4861-bbbe-657013126e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069485075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.3069485075
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.699347633
Short name T117
Test name
Test status
Simulation time 127363574843 ps
CPU time 1424.92 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:53:29 PM PDT 24
Peak memory 222052 kb
Host smart-ed996cba-12ff-4604-bbb7-007bea38bedb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699347633 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.699347633
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.edn_alert.3101199224
Short name T102
Test name
Test status
Simulation time 29954843 ps
CPU time 1.28 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 215068 kb
Host smart-3b462949-352e-461f-a702-40c0cd91a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101199224 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.3101199224
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.2204586009
Short name T304
Test name
Test status
Simulation time 15183213 ps
CPU time 0.99 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:21 PM PDT 24
Peak memory 206424 kb
Host smart-a888a6e2-c122-414a-9c1a-32bab3674da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204586009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2204586009
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_err.3045385652
Short name T54
Test name
Test status
Simulation time 18992295 ps
CPU time 1.2 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:28:20 PM PDT 24
Peak memory 223352 kb
Host smart-a6d267a4-2e59-4b07-b677-4a825bd1aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045385652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3045385652
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/31.edn_alert.1282626530
Short name T292
Test name
Test status
Simulation time 306368139 ps
CPU time 1.47 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 218000 kb
Host smart-754f1355-bb04-4aec-b556-3f72e8ff51c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282626530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1282626530
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2053222655
Short name T299
Test name
Test status
Simulation time 375504544 ps
CPU time 3.93 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 206316 kb
Host smart-d014925b-8d66-473e-be95-0b8da2ac6971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053222655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2053222655
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/128.edn_alert.3948377903
Short name T69
Test name
Test status
Simulation time 37054404 ps
CPU time 1.34 seconds
Started Jun 24 06:31:27 PM PDT 24
Finished Jun 24 06:31:29 PM PDT 24
Peak memory 215080 kb
Host smart-0b556004-e85a-4339-a832-ba45dfe8f082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948377903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.3948377903
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/47.edn_disable.3703457946
Short name T92
Test name
Test status
Simulation time 17057335 ps
CPU time 0.86 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 215672 kb
Host smart-4ff143c4-fc0a-41d4-83d0-aeb83ac9b8cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703457946 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3703457946
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3906181271
Short name T260
Test name
Test status
Simulation time 126688868 ps
CPU time 0.97 seconds
Started Jun 24 05:43:31 PM PDT 24
Finished Jun 24 05:43:33 PM PDT 24
Peak memory 206356 kb
Host smart-de18c1e7-6431-41f5-b9ce-c2fa71bb1f72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906181271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3906181271
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1173295095
Short name T134
Test name
Test status
Simulation time 59128603 ps
CPU time 1.19 seconds
Started Jun 24 06:29:42 PM PDT 24
Finished Jun 24 06:29:44 PM PDT 24
Peak memory 216196 kb
Host smart-f9f60654-5f53-4cd6-8ce3-e0c2d7f75162
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173295095 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1173295095
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.2205486500
Short name T291
Test name
Test status
Simulation time 102977551 ps
CPU time 1.31 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 215092 kb
Host smart-f093b230-8dcf-45b6-bce2-7e7fdfdbd350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205486500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2205486500
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.3170121359
Short name T201
Test name
Test status
Simulation time 18245633 ps
CPU time 0.82 seconds
Started Jun 24 06:28:59 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 215812 kb
Host smart-cff7ed9f-2555-48cc-85ba-ac2b6d3de988
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170121359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3170121359
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.1071280104
Short name T214
Test name
Test status
Simulation time 41567290 ps
CPU time 0.87 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:04 PM PDT 24
Peak memory 215688 kb
Host smart-2b18006a-8043-4986-889e-6ab8f0c3096d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071280104 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1071280104
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.863536484
Short name T163
Test name
Test status
Simulation time 31475914 ps
CPU time 1.22 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:26 PM PDT 24
Peak memory 216316 kb
Host smart-81c1b8b5-08ae-4552-8d23-e80e0d174fd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863536484 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.863536484
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/129.edn_alert.1780505431
Short name T90
Test name
Test status
Simulation time 30209906 ps
CPU time 1.3 seconds
Started Jun 24 06:31:27 PM PDT 24
Finished Jun 24 06:31:29 PM PDT 24
Peak memory 215140 kb
Host smart-15b2b201-5818-4751-a5d2-0a43ac98a635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780505431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.1780505431
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/72.edn_genbits.1083362640
Short name T318
Test name
Test status
Simulation time 33045689 ps
CPU time 1.32 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 219160 kb
Host smart-1d2f2150-1efd-4458-abc6-f85bf9edb14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083362640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1083362640
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1696459167
Short name T35
Test name
Test status
Simulation time 35819536838 ps
CPU time 816.57 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:43:40 PM PDT 24
Peak memory 222920 kb
Host smart-3bacebae-c5ca-4c32-a765-122dccfd3664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696459167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1696459167
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3744255771
Short name T194
Test name
Test status
Simulation time 78416281 ps
CPU time 1.13 seconds
Started Jun 24 06:31:30 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 217832 kb
Host smart-96ab91e1-463e-4aed-90d7-63f64c13a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744255771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3744255771
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1331596292
Short name T751
Test name
Test status
Simulation time 37709655 ps
CPU time 1.27 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 217572 kb
Host smart-37bdec34-4782-413d-809f-0fea412c5dd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331596292 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1331596292
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/193.edn_genbits.3085834369
Short name T313
Test name
Test status
Simulation time 49526716 ps
CPU time 1.4 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 219384 kb
Host smart-111b378f-814a-426b-903e-0c7d5f362faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085834369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3085834369
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3581245559
Short name T97
Test name
Test status
Simulation time 58025567 ps
CPU time 1.25 seconds
Started Jun 24 06:31:54 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 216472 kb
Host smart-b99296e0-f77c-4f6d-9780-63fd9cf89460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581245559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3581245559
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1627707435
Short name T285
Test name
Test status
Simulation time 79443394 ps
CPU time 1.14 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 218872 kb
Host smart-6f3896b6-1142-4bf9-9c23-6fc00fab35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627707435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1627707435
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/125.edn_alert.3127148453
Short name T305
Test name
Test status
Simulation time 27740992 ps
CPU time 1.21 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 217740 kb
Host smart-c59854ef-1154-4293-a5ad-ad71cc0d5add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127148453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3127148453
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert.2567072320
Short name T762
Test name
Test status
Simulation time 24782043 ps
CPU time 1.2 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 219152 kb
Host smart-39d299de-61e8-4528-b274-43f73649a645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567072320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2567072320
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/12.edn_intr.3827064295
Short name T32
Test name
Test status
Simulation time 34549380 ps
CPU time 0.92 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 214876 kb
Host smart-a5739ef4-fbd9-46ac-a9e2-11d279155e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827064295 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3827064295
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/9.edn_alert.946309582
Short name T104
Test name
Test status
Simulation time 226826859 ps
CPU time 1.21 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 221068 kb
Host smart-610dbb3a-3bde-4429-907e-a7aff5fdf468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946309582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.946309582
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/188.edn_alert.2853616460
Short name T196
Test name
Test status
Simulation time 78127062 ps
CPU time 1.15 seconds
Started Jun 24 06:32:01 PM PDT 24
Finished Jun 24 06:32:03 PM PDT 24
Peak memory 220228 kb
Host smart-f69620fa-acd1-4bd1-b079-d78d2530221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853616460 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2853616460
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.539671733
Short name T50
Test name
Test status
Simulation time 20825757 ps
CPU time 0.9 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:54 PM PDT 24
Peak memory 214808 kb
Host smart-36131cad-3a92-43ed-97ab-2293f0ea285c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539671733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.539671733
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.1291712468
Short name T29
Test name
Test status
Simulation time 20849770 ps
CPU time 1.1 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 215024 kb
Host smart-877775cd-b43c-44c4-8c1a-a8ea08afe48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291712468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1291712468
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/104.edn_alert.3438447209
Short name T166
Test name
Test status
Simulation time 50378354 ps
CPU time 1.25 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 218112 kb
Host smart-d4948b92-dcae-4983-8662-2a162f7c8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438447209 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.3438447209
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1323153535
Short name T226
Test name
Test status
Simulation time 12817656 ps
CPU time 0.93 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:03 PM PDT 24
Peak memory 215784 kb
Host smart-29773367-c797-48e2-b34b-b244d6cdfd6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323153535 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1323153535
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.4027525558
Short name T534
Test name
Test status
Simulation time 20630482 ps
CPU time 1.1 seconds
Started Jun 24 06:29:00 PM PDT 24
Finished Jun 24 06:29:02 PM PDT 24
Peak memory 219016 kb
Host smart-41308d8e-e041-4280-94f2-62ad4d8f5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027525558 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4027525558
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/113.edn_alert.1548012980
Short name T692
Test name
Test status
Simulation time 136371790 ps
CPU time 1.13 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 217964 kb
Host smart-23a41461-fe83-418e-95e3-66cc9d109905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548012980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1548012980
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/114.edn_alert.1445597958
Short name T94
Test name
Test status
Simulation time 75061856 ps
CPU time 1.1 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 218624 kb
Host smart-87893b89-9559-4ee8-9c5e-1cadb8d80e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445597958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.1445597958
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.2447949230
Short name T191
Test name
Test status
Simulation time 40443153 ps
CPU time 0.86 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 215684 kb
Host smart-1d9998b3-7867-4660-a9d4-e9ccd57d2b7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447949230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2447949230
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.192908530
Short name T168
Test name
Test status
Simulation time 36742366 ps
CPU time 1.37 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:46 PM PDT 24
Peak memory 216316 kb
Host smart-09a485bc-4e93-4bbb-9236-fd1711ed4740
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192908530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.192908530
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.3058933411
Short name T212
Test name
Test status
Simulation time 37230545 ps
CPU time 0.86 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 215812 kb
Host smart-0351aab6-8739-4866-b3a4-43586e813ad3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058933411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3058933411
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable.1912382326
Short name T216
Test name
Test status
Simulation time 18823343 ps
CPU time 0.86 seconds
Started Jun 24 06:30:09 PM PDT 24
Finished Jun 24 06:30:11 PM PDT 24
Peak memory 215684 kb
Host smart-368a1e6e-308d-4100-9b47-f2bd8ebacb3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912382326 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1912382326
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable.3433552672
Short name T203
Test name
Test status
Simulation time 18934154 ps
CPU time 0.86 seconds
Started Jun 24 06:28:41 PM PDT 24
Finished Jun 24 06:28:42 PM PDT 24
Peak memory 215676 kb
Host smart-460c96e7-822f-4070-9f44-028b6be607a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433552672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3433552672
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable.1455651177
Short name T202
Test name
Test status
Simulation time 23560215 ps
CPU time 0.94 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 215964 kb
Host smart-548ff6dd-51dd-4854-9649-a363138c8026
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455651177 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1455651177
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.3645512362
Short name T205
Test name
Test status
Simulation time 23898925 ps
CPU time 0.92 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 217620 kb
Host smart-07cb66eb-a336-4626-8d3a-82d9828de1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645512362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3645512362
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/1.edn_alert_test.2801502687
Short name T372
Test name
Test status
Simulation time 26475029 ps
CPU time 0.86 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:28 PM PDT 24
Peak memory 206152 kb
Host smart-691abfba-da24-42d8-839c-83d41ebe9d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801502687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2801502687
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/196.edn_alert.2407171287
Short name T965
Test name
Test status
Simulation time 29494585 ps
CPU time 1.32 seconds
Started Jun 24 06:32:01 PM PDT 24
Finished Jun 24 06:32:03 PM PDT 24
Peak memory 220160 kb
Host smart-2f9513f1-34c0-4f4b-bb0f-e16cacb7410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407171287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2407171287
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/221.edn_genbits.701326824
Short name T317
Test name
Test status
Simulation time 227207369 ps
CPU time 2.41 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 219284 kb
Host smart-800fb3a0-5567-43bc-b672-3746eeda1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701326824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.701326824
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/290.edn_genbits.61215249
Short name T315
Test name
Test status
Simulation time 153534238 ps
CPU time 1.5 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:18 PM PDT 24
Peak memory 218020 kb
Host smart-543c8cb6-01bd-47bd-ac0e-c00adace70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61215249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.61215249
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_genbits.3183235560
Short name T83
Test name
Test status
Simulation time 61240127 ps
CPU time 1.2 seconds
Started Jun 24 06:29:38 PM PDT 24
Finished Jun 24 06:29:41 PM PDT 24
Peak memory 217912 kb
Host smart-1fc652c7-7bc4-4811-aa47-60479684d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183235560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3183235560
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1637625908
Short name T105
Test name
Test status
Simulation time 52458779 ps
CPU time 0.84 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 214876 kb
Host smart-cc0c9d92-0634-42e6-810f-8740a8ffb47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637625908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1637625908
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2992589166
Short name T279
Test name
Test status
Simulation time 63654489 ps
CPU time 1.39 seconds
Started Jun 24 05:43:33 PM PDT 24
Finished Jun 24 05:43:36 PM PDT 24
Peak memory 206340 kb
Host smart-603b540f-45f4-427f-86cf-d27d5637bd4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992589166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2992589166
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1444685669
Short name T1038
Test name
Test status
Simulation time 427895555 ps
CPU time 2.21 seconds
Started Jun 24 05:43:24 PM PDT 24
Finished Jun 24 05:43:26 PM PDT 24
Peak memory 206680 kb
Host smart-9c062cec-5040-4b86-add8-a50018f1adc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444685669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1444685669
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_stress_all.2145233382
Short name T912
Test name
Test status
Simulation time 629709234 ps
CPU time 4.11 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:24 PM PDT 24
Peak memory 216616 kb
Host smart-be1f51e9-8c12-4186-a51b-f17a7cd6a30c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145233382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2145233382
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/101.edn_genbits.4147667839
Short name T346
Test name
Test status
Simulation time 787176782 ps
CPU time 7.17 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:27 PM PDT 24
Peak memory 219568 kb
Host smart-8153929b-e974-494c-a84e-95c49bf753ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147667839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.4147667839
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.736912738
Short name T122
Test name
Test status
Simulation time 29019282 ps
CPU time 1.25 seconds
Started Jun 24 06:31:17 PM PDT 24
Finished Jun 24 06:31:20 PM PDT 24
Peak memory 218568 kb
Host smart-9a9ca505-ce4a-4af5-80c8-d4da81559f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736912738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.736912738
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/106.edn_alert.744332055
Short name T121
Test name
Test status
Simulation time 80315810 ps
CPU time 1.27 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 219432 kb
Host smart-4a97fca5-0f42-445f-bd36-1994855eeefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744332055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.744332055
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.3077450402
Short name T755
Test name
Test status
Simulation time 59423284 ps
CPU time 1.59 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 217976 kb
Host smart-34492fed-f60a-4af4-a597-2bb01420864a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077450402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3077450402
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2676549774
Short name T330
Test name
Test status
Simulation time 54010495 ps
CPU time 1.24 seconds
Started Jun 24 06:31:21 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 216788 kb
Host smart-8ec8e42e-c6a2-47f9-96c6-22f9514180e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676549774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2676549774
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3856106146
Short name T343
Test name
Test status
Simulation time 66939292 ps
CPU time 1.55 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:40 PM PDT 24
Peak memory 217928 kb
Host smart-85f8d82a-79ec-4e47-ade5-f2bbe7ce304e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856106146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3856106146
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_genbits.904534531
Short name T331
Test name
Test status
Simulation time 91131069 ps
CPU time 1.17 seconds
Started Jun 24 06:29:07 PM PDT 24
Finished Jun 24 06:29:09 PM PDT 24
Peak memory 218304 kb
Host smart-929dbfc8-732f-4be7-9b0f-4d132e0b1b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904534531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.904534531
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.3849900734
Short name T322
Test name
Test status
Simulation time 132881253 ps
CPU time 1.63 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:06 PM PDT 24
Peak memory 218292 kb
Host smart-4bd0239e-77a5-408e-8db7-100ca0bcdb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849900734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3849900734
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1810561783
Short name T327
Test name
Test status
Simulation time 55819078 ps
CPU time 2.2 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 219508 kb
Host smart-6ab546f9-8cab-4240-ae9c-e536f33a4361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810561783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1810561783
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1851382682
Short name T858
Test name
Test status
Simulation time 39316268639 ps
CPU time 885.52 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:44:56 PM PDT 24
Peak memory 217964 kb
Host smart-a294348e-849d-456a-9e41-bb2bdd82aeab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851382682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1851382682
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1666300839
Short name T238
Test name
Test status
Simulation time 15515031570 ps
CPU time 339.65 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 217160 kb
Host smart-2ea495dc-0b0d-42e8-ad98-23851bb497b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666300839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1666300839
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_intr.1591073200
Short name T109
Test name
Test status
Simulation time 35409004 ps
CPU time 0.89 seconds
Started Jun 24 06:29:00 PM PDT 24
Finished Jun 24 06:29:02 PM PDT 24
Peak memory 214888 kb
Host smart-28e4b6bc-616b-4a95-9e28-b655c9ade528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591073200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1591073200
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/83.edn_genbits.318134123
Short name T398
Test name
Test status
Simulation time 58802267 ps
CPU time 2 seconds
Started Jun 24 06:30:59 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 219300 kb
Host smart-39fbd9b6-fb15-414a-9aa8-5b193821a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318134123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.318134123
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.715028563
Short name T1094
Test name
Test status
Simulation time 40531791 ps
CPU time 0.96 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:36 PM PDT 24
Peak memory 206332 kb
Host smart-07231520-ce52-4551-81fa-0410bffe391f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715028563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.715028563
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2584133819
Short name T1053
Test name
Test status
Simulation time 133364513 ps
CPU time 3.48 seconds
Started Jun 24 05:43:35 PM PDT 24
Finished Jun 24 05:43:39 PM PDT 24
Peak memory 206300 kb
Host smart-7411fb13-4de3-4d1b-b2dd-8ad33ede9696
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584133819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2584133819
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.613430325
Short name T1120
Test name
Test status
Simulation time 13734239 ps
CPU time 0.88 seconds
Started Jun 24 05:43:37 PM PDT 24
Finished Jun 24 05:43:38 PM PDT 24
Peak memory 206280 kb
Host smart-3b56c5a6-28c0-475f-86c5-b3d056d80979
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613430325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.613430325
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1236759683
Short name T1077
Test name
Test status
Simulation time 89094542 ps
CPU time 1.25 seconds
Started Jun 24 05:43:31 PM PDT 24
Finished Jun 24 05:43:32 PM PDT 24
Peak memory 214612 kb
Host smart-ed7f287f-7255-4da7-a979-c9c3fee43af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236759683 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1236759683
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1099602524
Short name T1085
Test name
Test status
Simulation time 47245067 ps
CPU time 0.9 seconds
Started Jun 24 05:43:25 PM PDT 24
Finished Jun 24 05:43:27 PM PDT 24
Peak memory 206316 kb
Host smart-fadebe9a-c8d8-4d32-8690-365a8b3dc772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099602524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1099602524
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.388389523
Short name T1030
Test name
Test status
Simulation time 16143809 ps
CPU time 0.94 seconds
Started Jun 24 05:43:32 PM PDT 24
Finished Jun 24 05:43:34 PM PDT 24
Peak memory 206316 kb
Host smart-11f29979-1a49-4085-b06f-227dccb5f73e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388389523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.388389523
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2637315518
Short name T999
Test name
Test status
Simulation time 154683912 ps
CPU time 1.83 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:37 PM PDT 24
Peak memory 214732 kb
Host smart-18ec6d65-a3fd-47c9-b507-c2347ba051b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637315518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2637315518
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1366696808
Short name T288
Test name
Test status
Simulation time 89387999 ps
CPU time 2.57 seconds
Started Jun 24 05:43:23 PM PDT 24
Finished Jun 24 05:43:26 PM PDT 24
Peak memory 206368 kb
Host smart-8754fa0c-b070-46ff-af61-89a520e0f79e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366696808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1366696808
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.366549624
Short name T1012
Test name
Test status
Simulation time 182377290 ps
CPU time 5.1 seconds
Started Jun 24 05:43:36 PM PDT 24
Finished Jun 24 05:43:42 PM PDT 24
Peak memory 206296 kb
Host smart-6ebf979e-a6b5-43c5-b443-466773e69c6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366549624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.366549624
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.120289441
Short name T270
Test name
Test status
Simulation time 15586771 ps
CPU time 0.94 seconds
Started Jun 24 05:43:40 PM PDT 24
Finished Jun 24 05:43:42 PM PDT 24
Peak memory 206304 kb
Host smart-ca3cacf1-6f19-450f-82ac-8cdb3058f6ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120289441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.120289441
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3236873673
Short name T998
Test name
Test status
Simulation time 30832960 ps
CPU time 1.54 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:43 PM PDT 24
Peak memory 222816 kb
Host smart-06faa3c9-e72b-4a8e-a67e-47f67c81bdba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236873673 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3236873673
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2206222552
Short name T271
Test name
Test status
Simulation time 41138338 ps
CPU time 0.86 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:36 PM PDT 24
Peak memory 206308 kb
Host smart-4946a7eb-db25-4669-a9d5-eb5be911be97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206222552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2206222552
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.892565424
Short name T1111
Test name
Test status
Simulation time 33896268 ps
CPU time 0.8 seconds
Started Jun 24 05:43:27 PM PDT 24
Finished Jun 24 05:43:28 PM PDT 24
Peak memory 206232 kb
Host smart-b44c7879-b1f9-464d-9d41-2f68601b21af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892565424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.892565424
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4166087013
Short name T1125
Test name
Test status
Simulation time 20775650 ps
CPU time 1.07 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206500 kb
Host smart-588c9ad3-81d6-43b6-ae6f-bd5148a11f7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166087013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.4166087013
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.860307183
Short name T1045
Test name
Test status
Simulation time 122916111 ps
CPU time 3.02 seconds
Started Jun 24 05:43:35 PM PDT 24
Finished Jun 24 05:43:39 PM PDT 24
Peak memory 222884 kb
Host smart-82f54337-6d7b-4fd6-a630-1ee91b50c786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860307183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.860307183
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3480644671
Short name T1118
Test name
Test status
Simulation time 47038170 ps
CPU time 1.25 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 214640 kb
Host smart-0cae33b1-5e3a-433d-b27c-d5190e177796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480644671 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3480644671
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1402679035
Short name T269
Test name
Test status
Simulation time 21389191 ps
CPU time 0.81 seconds
Started Jun 24 05:44:24 PM PDT 24
Finished Jun 24 05:44:25 PM PDT 24
Peak memory 206232 kb
Host smart-9375bc94-5e28-4cd2-ba53-6c88705148e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402679035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1402679035
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2994752946
Short name T1014
Test name
Test status
Simulation time 56569613 ps
CPU time 0.82 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:43 PM PDT 24
Peak memory 206460 kb
Host smart-c80ec025-dbf5-49a2-96c4-15237d232e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994752946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2994752946
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1497579347
Short name T1091
Test name
Test status
Simulation time 28298440 ps
CPU time 1.17 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 206404 kb
Host smart-5d16cc2d-d740-43ec-bede-83dea093c602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497579347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1497579347
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2671198957
Short name T1117
Test name
Test status
Simulation time 97417181 ps
CPU time 2.38 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:50 PM PDT 24
Peak memory 214700 kb
Host smart-de0cf630-ea76-4b0e-9229-c873f0faf3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671198957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2671198957
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3645084617
Short name T1068
Test name
Test status
Simulation time 339856668 ps
CPU time 2.46 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206344 kb
Host smart-188ee94c-40ea-419e-ba7c-3bb351c99254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645084617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3645084617
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3603545105
Short name T1090
Test name
Test status
Simulation time 163841315 ps
CPU time 1.24 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:45 PM PDT 24
Peak memory 214660 kb
Host smart-4b5351b9-4e96-4e01-b8cb-a81a34891bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603545105 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3603545105
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2627294690
Short name T1065
Test name
Test status
Simulation time 31091323 ps
CPU time 1 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:45 PM PDT 24
Peak memory 206304 kb
Host smart-059d4b1e-9560-492f-803c-07b8e168e37b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627294690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2627294690
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2287969003
Short name T1023
Test name
Test status
Simulation time 18210321 ps
CPU time 0.84 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206292 kb
Host smart-98382cee-3817-4046-bd0b-130aef26fa8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287969003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2287969003
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2588314843
Short name T1115
Test name
Test status
Simulation time 156670506 ps
CPU time 1.1 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:19 PM PDT 24
Peak memory 206372 kb
Host smart-882c6a94-c2b8-49a4-973a-40b2148f5e94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588314843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2588314843
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.941534775
Short name T1024
Test name
Test status
Simulation time 203199515 ps
CPU time 3.33 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 214612 kb
Host smart-28430010-2753-4bdd-b914-0aa21ef352d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941534775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.941534775
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1084462428
Short name T1052
Test name
Test status
Simulation time 242300932 ps
CPU time 2.12 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206456 kb
Host smart-c90a79a9-eb03-45cb-a49d-c57ae1276a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084462428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1084462428
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1625050880
Short name T1055
Test name
Test status
Simulation time 77977268 ps
CPU time 1.2 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 214680 kb
Host smart-8eb7652a-1256-42e1-9dc4-3ca4a74f9d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625050880 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1625050880
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2589168448
Short name T277
Test name
Test status
Simulation time 15890388 ps
CPU time 0.93 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 206280 kb
Host smart-335fa92b-8b29-4f79-898f-3644f8b3b132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589168448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2589168448
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1612405471
Short name T1022
Test name
Test status
Simulation time 25539815 ps
CPU time 0.86 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206296 kb
Host smart-790d2059-4002-4319-9e58-8a5d27312245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612405471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1612405471
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3632040076
Short name T1073
Test name
Test status
Simulation time 55571188 ps
CPU time 1.3 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206356 kb
Host smart-dce09c39-f699-4989-a3bc-a71731283fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632040076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3632040076
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1455637870
Short name T1027
Test name
Test status
Simulation time 31544469 ps
CPU time 1.83 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 214668 kb
Host smart-a00556fd-657a-42c4-acb5-7b89f1740806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455637870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1455637870
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.887011343
Short name T1074
Test name
Test status
Simulation time 180592709 ps
CPU time 2.5 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206428 kb
Host smart-dc701fe0-1cb0-41c9-8730-3a012c883aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887011343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.887011343
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2078148079
Short name T1009
Test name
Test status
Simulation time 53469830 ps
CPU time 1.74 seconds
Started Jun 24 05:43:59 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 214772 kb
Host smart-03392fb4-b951-40d0-96a5-4e2bc8d52522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078148079 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2078148079
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.726994815
Short name T1062
Test name
Test status
Simulation time 17848960 ps
CPU time 0.86 seconds
Started Jun 24 05:43:52 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 206200 kb
Host smart-d6fcf379-0816-4535-8ef8-52f0476a7572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726994815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.726994815
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1687036290
Short name T1084
Test name
Test status
Simulation time 22675395 ps
CPU time 0.84 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206324 kb
Host smart-06f47535-e04f-40ab-ac53-0209f4140e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687036290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1687036290
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2779932863
Short name T1072
Test name
Test status
Simulation time 76687667 ps
CPU time 1.1 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 206456 kb
Host smart-9f0607df-9353-4c84-aacd-3dbb397ea474
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779932863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2779932863
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2609662035
Short name T1112
Test name
Test status
Simulation time 288036165 ps
CPU time 4.38 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 214636 kb
Host smart-f8c18827-9d94-4947-8234-c061b51bce4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609662035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2609662035
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2584778482
Short name T1029
Test name
Test status
Simulation time 44462287 ps
CPU time 1.57 seconds
Started Jun 24 05:43:39 PM PDT 24
Finished Jun 24 05:43:41 PM PDT 24
Peak memory 206372 kb
Host smart-dfd48a8e-8e5f-44ea-9695-252b396177fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584778482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2584778482
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.408789420
Short name T1034
Test name
Test status
Simulation time 22774409 ps
CPU time 1.34 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 214620 kb
Host smart-c58aae37-13c7-407c-b8b4-050db2f8a70c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408789420 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.408789420
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.702121265
Short name T1081
Test name
Test status
Simulation time 15124624 ps
CPU time 0.85 seconds
Started Jun 24 05:43:54 PM PDT 24
Finished Jun 24 05:43:58 PM PDT 24
Peak memory 206304 kb
Host smart-4905dc50-73a1-4764-9fef-ea77ca9015dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702121265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.702121265
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3062092691
Short name T1010
Test name
Test status
Simulation time 41634093 ps
CPU time 0.79 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 206212 kb
Host smart-92fe79ed-bbe1-4126-8065-2a177ec352a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062092691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3062092691
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.63999158
Short name T1076
Test name
Test status
Simulation time 71163153 ps
CPU time 1.08 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 206376 kb
Host smart-23369fe0-fe83-4e66-868a-6138369a56b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63999158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_out
standing.63999158
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1412018710
Short name T1086
Test name
Test status
Simulation time 719601279 ps
CPU time 2.78 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 222788 kb
Host smart-1aa2be7a-07f2-4423-b4ab-45ea36319be8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412018710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1412018710
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.941481645
Short name T1110
Test name
Test status
Simulation time 111736477 ps
CPU time 2.79 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206440 kb
Host smart-942d2c75-364b-4146-9fc5-b2d7a1ae883d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941481645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.941481645
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3368468902
Short name T1078
Test name
Test status
Simulation time 155588402 ps
CPU time 1.17 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 214560 kb
Host smart-7ca76c85-613e-49f5-85d4-b267ce5c9a10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368468902 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3368468902
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3410673007
Short name T272
Test name
Test status
Simulation time 25162598 ps
CPU time 0.89 seconds
Started Jun 24 05:43:42 PM PDT 24
Finished Jun 24 05:43:51 PM PDT 24
Peak memory 206288 kb
Host smart-9a3f0c55-bbb6-4930-a4b7-47cbe23d4384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410673007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3410673007
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3695058948
Short name T1005
Test name
Test status
Simulation time 12975196 ps
CPU time 0.87 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206312 kb
Host smart-ed118941-877b-43d2-8cf6-50de109f9568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695058948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3695058948
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2592137307
Short name T276
Test name
Test status
Simulation time 17219485 ps
CPU time 1.09 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:51 PM PDT 24
Peak memory 206352 kb
Host smart-d73788ce-0e40-40fb-b671-826ffe73d6cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592137307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2592137307
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4100694626
Short name T1100
Test name
Test status
Simulation time 75690442 ps
CPU time 2.74 seconds
Started Jun 24 05:43:42 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 214740 kb
Host smart-aa902eda-3102-4b45-b3dd-93edeb2e1c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100694626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4100694626
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2919723620
Short name T1103
Test name
Test status
Simulation time 173267578 ps
CPU time 2.06 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206464 kb
Host smart-0ca2fec9-9e47-4629-81e8-b7ead0a73c50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919723620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2919723620
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2644271340
Short name T1098
Test name
Test status
Simulation time 64987803 ps
CPU time 1.28 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:51 PM PDT 24
Peak memory 214664 kb
Host smart-36b9605d-ccb4-4b37-96da-f1042abe549d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644271340 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2644271340
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1773994520
Short name T268
Test name
Test status
Simulation time 19853742 ps
CPU time 1.01 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206068 kb
Host smart-0d83437e-a705-4667-a259-02197d8fcd09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773994520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1773994520
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2745829472
Short name T1124
Test name
Test status
Simulation time 14300942 ps
CPU time 0.89 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206312 kb
Host smart-11d86cd8-c84c-4266-af9d-9132c19f1072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745829472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2745829472
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1004996403
Short name T1126
Test name
Test status
Simulation time 59994789 ps
CPU time 1.32 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 206428 kb
Host smart-37c4403d-799c-4679-b948-0403694c1943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004996403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1004996403
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3887577762
Short name T1127
Test name
Test status
Simulation time 120917940 ps
CPU time 4 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 214644 kb
Host smart-5759a7aa-fac8-48c3-8c9f-3098b2b1702d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887577762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3887577762
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1183455667
Short name T289
Test name
Test status
Simulation time 632355005 ps
CPU time 3.33 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206112 kb
Host smart-bbc7a45d-8914-4865-bf1f-585c0837f190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183455667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1183455667
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.319902121
Short name T1059
Test name
Test status
Simulation time 48745467 ps
CPU time 0.93 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:42 PM PDT 24
Peak memory 206656 kb
Host smart-ad80690e-d2f4-4783-b6b8-a971f50ca25c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319902121 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.319902121
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2109934039
Short name T280
Test name
Test status
Simulation time 33700405 ps
CPU time 0.81 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206212 kb
Host smart-2a20fa92-30b9-4c27-9cc9-12946e95cea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109934039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2109934039
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2888029228
Short name T1107
Test name
Test status
Simulation time 22684583 ps
CPU time 0.84 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:50 PM PDT 24
Peak memory 206316 kb
Host smart-ba22fc33-2032-41b9-b231-926187c24e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888029228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2888029228
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.231025511
Short name T1095
Test name
Test status
Simulation time 108141118 ps
CPU time 1.32 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 206592 kb
Host smart-9759a8ce-2a99-4fa2-a9af-03c4c2bc9b51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231025511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.231025511
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.310940285
Short name T996
Test name
Test status
Simulation time 49642585 ps
CPU time 2.43 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 214592 kb
Host smart-92494e49-965a-4651-8f22-ef6134e0fc09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310940285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.310940285
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3610842549
Short name T298
Test name
Test status
Simulation time 170785013 ps
CPU time 2.48 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206368 kb
Host smart-946f82f7-ad82-4483-8829-e5d3aac37dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610842549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3610842549
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2520496739
Short name T995
Test name
Test status
Simulation time 93397923 ps
CPU time 1.28 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 214648 kb
Host smart-54a0ab31-980b-48d6-9b3a-825eec40ea3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520496739 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2520496739
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1963385258
Short name T1058
Test name
Test status
Simulation time 33651502 ps
CPU time 0.87 seconds
Started Jun 24 05:43:37 PM PDT 24
Finished Jun 24 05:43:39 PM PDT 24
Peak memory 206220 kb
Host smart-64ee5684-eaa4-428e-a1de-6bcb474049ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963385258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1963385258
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1072254519
Short name T1051
Test name
Test status
Simulation time 32073128 ps
CPU time 0.8 seconds
Started Jun 24 05:43:51 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206232 kb
Host smart-f7b44a43-72b8-4efc-a90c-a3383c3a864e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072254519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1072254519
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.399189158
Short name T273
Test name
Test status
Simulation time 28666435 ps
CPU time 1.26 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206516 kb
Host smart-7c8b40f5-527e-47cc-9d3e-46b29a75c71e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399189158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.399189158
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.84041502
Short name T1070
Test name
Test status
Simulation time 36176765 ps
CPU time 1.54 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:47 PM PDT 24
Peak memory 214596 kb
Host smart-7104c98a-b4d8-4a64-bf64-64c1983de748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84041502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.84041502
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.242839788
Short name T1025
Test name
Test status
Simulation time 91960565 ps
CPU time 2.4 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 214580 kb
Host smart-a39a465f-f1aa-4f15-8dce-485145b7ce9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242839788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.242839788
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2003866918
Short name T1050
Test name
Test status
Simulation time 15509188 ps
CPU time 1.12 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 217000 kb
Host smart-f8292c73-66dd-4c8e-acfa-841043e4b064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003866918 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2003866918
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2676248521
Short name T267
Test name
Test status
Simulation time 23983566 ps
CPU time 0.94 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206304 kb
Host smart-d804e4c4-2e38-4d36-8803-9e02a919c698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676248521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2676248521
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2229743756
Short name T1069
Test name
Test status
Simulation time 23879555 ps
CPU time 0.79 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206220 kb
Host smart-934eca67-0398-4dc4-85d9-13228b064cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229743756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2229743756
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3417416432
Short name T275
Test name
Test status
Simulation time 30329479 ps
CPU time 1.09 seconds
Started Jun 24 05:43:56 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 206472 kb
Host smart-eb35a50f-b78b-4596-b21e-7077fc406b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417416432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3417416432
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1319116682
Short name T993
Test name
Test status
Simulation time 166736063 ps
CPU time 3.4 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 214608 kb
Host smart-c5780f08-4d70-4db6-9f43-519eff8ebbf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319116682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1319116682
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.4110793925
Short name T1057
Test name
Test status
Simulation time 229002726 ps
CPU time 2.34 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:07 PM PDT 24
Peak memory 206396 kb
Host smart-16ebc03c-4363-4fea-abdd-4498fb838587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110793925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.4110793925
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3957978777
Short name T266
Test name
Test status
Simulation time 32485689 ps
CPU time 1.26 seconds
Started Jun 24 05:43:33 PM PDT 24
Finished Jun 24 05:43:36 PM PDT 24
Peak memory 206456 kb
Host smart-44a3def5-e3c0-4fec-86af-0344edf82f50
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957978777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3957978777
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2300196442
Short name T1096
Test name
Test status
Simulation time 531390730 ps
CPU time 2.25 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 206312 kb
Host smart-60459f5d-0b89-4c64-abd2-1afdc032a88a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300196442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2300196442
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.198761966
Short name T263
Test name
Test status
Simulation time 16408917 ps
CPU time 0.91 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:45 PM PDT 24
Peak memory 206276 kb
Host smart-b2fb6f8d-9994-4ce8-b793-010a7724b8f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198761966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.198761966
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2412041586
Short name T1031
Test name
Test status
Simulation time 100372585 ps
CPU time 1.55 seconds
Started Jun 24 05:43:33 PM PDT 24
Finished Jun 24 05:43:35 PM PDT 24
Peak memory 214544 kb
Host smart-5f19159b-4230-4807-84f8-0370bbc11b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412041586 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2412041586
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1292482222
Short name T1114
Test name
Test status
Simulation time 23450232 ps
CPU time 0.87 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:43 PM PDT 24
Peak memory 206312 kb
Host smart-eccabbf2-50a1-424f-a283-5da26201269b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292482222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1292482222
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.904051897
Short name T1040
Test name
Test status
Simulation time 16483580 ps
CPU time 0.93 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206312 kb
Host smart-e2aa942f-9cb1-482c-a16e-0a04ea0e91d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904051897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.904051897
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1581917504
Short name T1079
Test name
Test status
Simulation time 18240993 ps
CPU time 1.13 seconds
Started Jun 24 05:43:42 PM PDT 24
Finished Jun 24 05:43:44 PM PDT 24
Peak memory 206380 kb
Host smart-f69bbc3a-649c-4603-a699-5c129eb93014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581917504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1581917504
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1881467324
Short name T1129
Test name
Test status
Simulation time 606036550 ps
CPU time 4.57 seconds
Started Jun 24 05:43:36 PM PDT 24
Finished Jun 24 05:43:41 PM PDT 24
Peak memory 214788 kb
Host smart-92a4cda0-ef2b-48af-aaf1-930989b9d4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881467324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1881467324
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3418832039
Short name T1066
Test name
Test status
Simulation time 102472434 ps
CPU time 2.46 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:09 PM PDT 24
Peak memory 206444 kb
Host smart-2e6446f4-a044-4cf1-a15d-3c0c7324f4ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418832039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3418832039
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2404703321
Short name T1049
Test name
Test status
Simulation time 14455430 ps
CPU time 0.9 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 206272 kb
Host smart-d1dad871-7954-488a-b868-24fd8f425e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404703321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2404703321
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1464463823
Short name T1067
Test name
Test status
Simulation time 11736477 ps
CPU time 0.88 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:54 PM PDT 24
Peak memory 206316 kb
Host smart-8e387f3c-f8e1-479e-8158-fc972c474ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464463823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1464463823
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3558252671
Short name T1088
Test name
Test status
Simulation time 18660003 ps
CPU time 0.9 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206304 kb
Host smart-70acb6de-6849-4a58-bbd8-9c11a6604dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558252671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3558252671
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3443146972
Short name T1082
Test name
Test status
Simulation time 13109274 ps
CPU time 0.86 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206308 kb
Host smart-2264b8d6-74bb-4ad1-b10d-844d927524b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443146972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3443146972
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4131353700
Short name T997
Test name
Test status
Simulation time 21964542 ps
CPU time 0.84 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206288 kb
Host smart-0985334f-58f2-4d56-88b0-ebe7a0d97a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131353700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4131353700
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1987752749
Short name T1037
Test name
Test status
Simulation time 14510962 ps
CPU time 0.88 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206312 kb
Host smart-5baec3bf-71e6-496b-99d9-b47aec1be75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987752749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1987752749
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.127142752
Short name T1087
Test name
Test status
Simulation time 33539795 ps
CPU time 0.88 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206220 kb
Host smart-aedbdbd1-1dc3-41ab-a9b7-57eda9ff9e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127142752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.127142752
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.688856702
Short name T1035
Test name
Test status
Simulation time 14342246 ps
CPU time 0.89 seconds
Started Jun 24 05:44:12 PM PDT 24
Finished Jun 24 05:44:15 PM PDT 24
Peak memory 206312 kb
Host smart-5067b844-fcae-4d7f-ba52-c79c23b543f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688856702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.688856702
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1745223765
Short name T1113
Test name
Test status
Simulation time 34976085 ps
CPU time 0.82 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206176 kb
Host smart-a3308f01-6192-4aec-b0ca-492e6f902a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745223765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1745223765
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1686874903
Short name T1043
Test name
Test status
Simulation time 37423288 ps
CPU time 0.82 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206312 kb
Host smart-d55655d8-71da-4d7d-a3af-4078491d6118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686874903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1686874903
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2858333782
Short name T265
Test name
Test status
Simulation time 71312427 ps
CPU time 1.56 seconds
Started Jun 24 05:43:39 PM PDT 24
Finished Jun 24 05:43:41 PM PDT 24
Peak memory 206396 kb
Host smart-9474281f-9242-4793-adee-e5a336327d96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858333782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2858333782
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1303092734
Short name T1016
Test name
Test status
Simulation time 363636198 ps
CPU time 2.94 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206320 kb
Host smart-d87e010c-7bb5-4835-8776-7a14b312c4d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303092734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1303092734
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2343589925
Short name T262
Test name
Test status
Simulation time 15976321 ps
CPU time 1.04 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:51 PM PDT 24
Peak memory 206312 kb
Host smart-bc59ed48-e433-4da8-95d3-03b5f98aea0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343589925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2343589925
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4016961004
Short name T1071
Test name
Test status
Simulation time 40214764 ps
CPU time 1.43 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:37 PM PDT 24
Peak memory 214852 kb
Host smart-a631b3f1-1182-4e6e-8851-30811f771a19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016961004 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4016961004
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2451046658
Short name T1092
Test name
Test status
Simulation time 39418685 ps
CPU time 0.89 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:36 PM PDT 24
Peak memory 206224 kb
Host smart-2f3943e2-58cf-455f-8923-87212d48550d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451046658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2451046658
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3241914286
Short name T1004
Test name
Test status
Simulation time 115698602 ps
CPU time 0.92 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 206396 kb
Host smart-3da1ff26-e55f-43e4-aa27-caabf7f5d352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241914286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3241914286
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2595353655
Short name T281
Test name
Test status
Simulation time 23599088 ps
CPU time 0.96 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 206404 kb
Host smart-edbd8ea5-b50e-4a5c-9b25-5480c7fcf304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595353655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2595353655
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.255185525
Short name T1032
Test name
Test status
Simulation time 158339154 ps
CPU time 4.55 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:48 PM PDT 24
Peak memory 214636 kb
Host smart-76c9364b-c080-48eb-a120-a7c044ab30cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255185525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.255185525
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1610541595
Short name T1036
Test name
Test status
Simulation time 167325425 ps
CPU time 1.48 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206376 kb
Host smart-44ea968f-4f56-40c1-b517-56f4d0a002ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610541595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1610541595
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2855980045
Short name T1013
Test name
Test status
Simulation time 14140389 ps
CPU time 0.87 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:43:58 PM PDT 24
Peak memory 206312 kb
Host smart-2297e25f-9276-4140-bc35-436a5c7bb6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855980045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2855980045
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2857758626
Short name T1046
Test name
Test status
Simulation time 17915879 ps
CPU time 0.96 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206312 kb
Host smart-f5120842-220a-4e93-a977-4bec98e0efec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857758626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2857758626
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1813549947
Short name T1003
Test name
Test status
Simulation time 18765959 ps
CPU time 0.91 seconds
Started Jun 24 05:43:53 PM PDT 24
Finished Jun 24 05:43:58 PM PDT 24
Peak memory 206320 kb
Host smart-60ccbc7e-92a6-4f7a-9f17-8d254c7bb5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813549947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1813549947
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2015895928
Short name T1123
Test name
Test status
Simulation time 43652525 ps
CPU time 0.88 seconds
Started Jun 24 05:43:49 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 206284 kb
Host smart-2a8ec9e9-c99a-4f0c-8a56-f25343bd7521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015895928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2015895928
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3332020472
Short name T1102
Test name
Test status
Simulation time 22183986 ps
CPU time 0.83 seconds
Started Jun 24 05:44:13 PM PDT 24
Finished Jun 24 05:44:16 PM PDT 24
Peak memory 206512 kb
Host smart-9a867fad-98a6-4799-96ac-e9a1285444f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332020472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3332020472
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.808109601
Short name T1006
Test name
Test status
Simulation time 20087930 ps
CPU time 0.84 seconds
Started Jun 24 05:44:09 PM PDT 24
Finished Jun 24 05:44:11 PM PDT 24
Peak memory 206308 kb
Host smart-43219f18-84b6-4b86-b51b-a1e41d898096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808109601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.808109601
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3822824560
Short name T1128
Test name
Test status
Simulation time 28544141 ps
CPU time 0.87 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:50 PM PDT 24
Peak memory 206312 kb
Host smart-a8cd08b5-ab47-4642-a3cc-2f1687441212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822824560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3822824560
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1644632012
Short name T994
Test name
Test status
Simulation time 81177856 ps
CPU time 0.79 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:50 PM PDT 24
Peak memory 206224 kb
Host smart-2d32c7cd-d865-441c-986d-b95172ef5632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644632012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1644632012
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1710692472
Short name T1104
Test name
Test status
Simulation time 18545852 ps
CPU time 0.9 seconds
Started Jun 24 05:43:51 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206312 kb
Host smart-79cd0165-63b5-4a4e-87c1-37c88ab4955a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710692472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1710692472
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3640071012
Short name T1109
Test name
Test status
Simulation time 45355240 ps
CPU time 0.86 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:06 PM PDT 24
Peak memory 206252 kb
Host smart-6b1022ad-b932-4ace-becc-184b37271db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640071012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3640071012
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2229743374
Short name T264
Test name
Test status
Simulation time 56410536 ps
CPU time 1.2 seconds
Started Jun 24 05:43:23 PM PDT 24
Finished Jun 24 05:43:25 PM PDT 24
Peak memory 206300 kb
Host smart-13fbec58-3f9a-4218-bccc-2df868c81400
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229743374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2229743374
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3101583162
Short name T1105
Test name
Test status
Simulation time 34083563 ps
CPU time 2.03 seconds
Started Jun 24 05:43:45 PM PDT 24
Finished Jun 24 05:43:49 PM PDT 24
Peak memory 206392 kb
Host smart-29d0a575-b9ea-4ce3-8e2f-f0dc7ef8b23f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101583162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3101583162
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.946442521
Short name T1042
Test name
Test status
Simulation time 16185805 ps
CPU time 0.9 seconds
Started Jun 24 05:43:34 PM PDT 24
Finished Jun 24 05:43:35 PM PDT 24
Peak memory 206300 kb
Host smart-1de83495-58e7-4318-816f-dc60c57068e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946442521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.946442521
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1413709931
Short name T1002
Test name
Test status
Simulation time 107795303 ps
CPU time 1.12 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 216920 kb
Host smart-a537f8d0-4525-434a-8890-41f4b6d62bb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413709931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1413709931
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4207214549
Short name T1121
Test name
Test status
Simulation time 33687700 ps
CPU time 0.85 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 206280 kb
Host smart-7fda447a-64c2-4f94-976d-88f9edd3387c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207214549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4207214549
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1020768470
Short name T1000
Test name
Test status
Simulation time 142580127 ps
CPU time 0.87 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206308 kb
Host smart-d49ef81b-e740-4957-b2cd-72cea572a12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020768470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1020768470
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1589293265
Short name T1063
Test name
Test status
Simulation time 50699409 ps
CPU time 1.05 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 206368 kb
Host smart-159697c4-e7be-432b-afcf-cc2e15441601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589293265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1589293265
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3624527781
Short name T1080
Test name
Test status
Simulation time 202761102 ps
CPU time 2.91 seconds
Started Jun 24 05:43:40 PM PDT 24
Finished Jun 24 05:43:43 PM PDT 24
Peak memory 214608 kb
Host smart-d5bb3d2a-d801-4f94-886d-56f7257496ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624527781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3624527781
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.545942069
Short name T1047
Test name
Test status
Simulation time 12957767 ps
CPU time 0.88 seconds
Started Jun 24 05:44:00 PM PDT 24
Finished Jun 24 05:44:03 PM PDT 24
Peak memory 206252 kb
Host smart-5ea918ff-7a44-4fe5-af07-a5a4ea38f601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545942069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.545942069
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3114173721
Short name T1018
Test name
Test status
Simulation time 15860076 ps
CPU time 0.93 seconds
Started Jun 24 05:44:04 PM PDT 24
Finished Jun 24 05:44:06 PM PDT 24
Peak memory 206312 kb
Host smart-e2ed6c04-61df-4ce7-bc7a-b0a9225c3c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114173721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3114173721
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2260415407
Short name T1101
Test name
Test status
Simulation time 50095791 ps
CPU time 0.93 seconds
Started Jun 24 05:44:11 PM PDT 24
Finished Jun 24 05:44:13 PM PDT 24
Peak memory 206312 kb
Host smart-9c7b1e0e-6067-4b92-839d-decdb6dbe2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260415407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2260415407
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3519537994
Short name T1048
Test name
Test status
Simulation time 13691367 ps
CPU time 0.89 seconds
Started Jun 24 05:44:07 PM PDT 24
Finished Jun 24 05:44:09 PM PDT 24
Peak memory 206308 kb
Host smart-f602431d-61a1-44be-afdf-b28dc294d7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519537994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3519537994
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4284506429
Short name T1064
Test name
Test status
Simulation time 114106877 ps
CPU time 0.86 seconds
Started Jun 24 05:44:01 PM PDT 24
Finished Jun 24 05:44:03 PM PDT 24
Peak memory 206232 kb
Host smart-4e2e222c-9f2b-4ebd-96a8-6bd902259ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284506429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4284506429
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1108823454
Short name T1033
Test name
Test status
Simulation time 29429093 ps
CPU time 0.95 seconds
Started Jun 24 05:44:00 PM PDT 24
Finished Jun 24 05:44:02 PM PDT 24
Peak memory 206260 kb
Host smart-233a5382-bfe9-4e80-b4a2-72717bb4d827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108823454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1108823454
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1941462022
Short name T1122
Test name
Test status
Simulation time 18431300 ps
CPU time 0.97 seconds
Started Jun 24 05:44:15 PM PDT 24
Finished Jun 24 05:44:18 PM PDT 24
Peak memory 206288 kb
Host smart-cc8af85f-ab78-41ce-b66d-51694f50dba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941462022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1941462022
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3239422056
Short name T1017
Test name
Test status
Simulation time 51327614 ps
CPU time 0.9 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206536 kb
Host smart-ae920a40-56fa-4589-a180-90d4c03dcdef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239422056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3239422056
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1966818798
Short name T1007
Test name
Test status
Simulation time 27886091 ps
CPU time 0.9 seconds
Started Jun 24 05:44:07 PM PDT 24
Finished Jun 24 05:44:08 PM PDT 24
Peak memory 206312 kb
Host smart-78412bf4-d03b-4b5a-8828-9b494fcfc3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966818798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1966818798
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3048357866
Short name T1001
Test name
Test status
Simulation time 14004452 ps
CPU time 0.92 seconds
Started Jun 24 05:43:53 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 206376 kb
Host smart-86824841-9f01-4ba1-8d4a-47de318fdda5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048357866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3048357866
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.106525186
Short name T1021
Test name
Test status
Simulation time 27859463 ps
CPU time 1.29 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:45 PM PDT 24
Peak memory 214608 kb
Host smart-9eb27e7c-ef02-43d6-a03b-965060cf1d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106525186 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.106525186
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2081634726
Short name T1116
Test name
Test status
Simulation time 30271272 ps
CPU time 0.85 seconds
Started Jun 24 05:43:38 PM PDT 24
Finished Jun 24 05:43:40 PM PDT 24
Peak memory 206176 kb
Host smart-6ccb966f-9689-441a-b495-10b643ece89d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081634726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2081634726
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4016642770
Short name T1011
Test name
Test status
Simulation time 11001415 ps
CPU time 0.81 seconds
Started Jun 24 05:43:42 PM PDT 24
Finished Jun 24 05:43:44 PM PDT 24
Peak memory 206304 kb
Host smart-ca3b9315-735b-4a55-b787-f3fbdb9a636c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016642770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4016642770
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2521081138
Short name T274
Test name
Test status
Simulation time 38469274 ps
CPU time 1.48 seconds
Started Jun 24 05:43:35 PM PDT 24
Finished Jun 24 05:43:38 PM PDT 24
Peak memory 206500 kb
Host smart-b54326fb-20a3-4691-a74f-47f687743ee3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521081138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2521081138
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.523227945
Short name T1119
Test name
Test status
Simulation time 917730279 ps
CPU time 3.62 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 219304 kb
Host smart-cbc50d12-ba24-434e-80cf-311a4a5b4d88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523227945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.523227945
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1367388085
Short name T300
Test name
Test status
Simulation time 90503473 ps
CPU time 2.61 seconds
Started Jun 24 05:43:36 PM PDT 24
Finished Jun 24 05:43:39 PM PDT 24
Peak memory 206572 kb
Host smart-a040cbb5-67af-4dc9-be62-cb7cc3cf2ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367388085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1367388085
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.880389733
Short name T1060
Test name
Test status
Simulation time 52827618 ps
CPU time 1.32 seconds
Started Jun 24 05:43:51 PM PDT 24
Finished Jun 24 05:43:57 PM PDT 24
Peak memory 214692 kb
Host smart-2193cd91-9a30-4512-836e-b17603362859
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880389733 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.880389733
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1277271213
Short name T1106
Test name
Test status
Simulation time 15130686 ps
CPU time 0.91 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206304 kb
Host smart-8d90e253-cbd6-40a1-8ee3-066b5cd5f525
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277271213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1277271213
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1203916758
Short name T1015
Test name
Test status
Simulation time 13406180 ps
CPU time 0.88 seconds
Started Jun 24 05:43:42 PM PDT 24
Finished Jun 24 05:43:44 PM PDT 24
Peak memory 206260 kb
Host smart-a924cc35-f6cb-4b50-bb89-298f1cb91aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203916758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1203916758
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.204021532
Short name T261
Test name
Test status
Simulation time 35045870 ps
CPU time 1.28 seconds
Started Jun 24 05:43:37 PM PDT 24
Finished Jun 24 05:43:39 PM PDT 24
Peak memory 206348 kb
Host smart-3213634f-9290-45b8-9b91-eff7e5e59817
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204021532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.204021532
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2733568021
Short name T1054
Test name
Test status
Simulation time 128121394 ps
CPU time 3.74 seconds
Started Jun 24 05:43:31 PM PDT 24
Finished Jun 24 05:43:35 PM PDT 24
Peak memory 214620 kb
Host smart-bbc1cfd6-64eb-4b25-b4db-9ce3cb4b046f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733568021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2733568021
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.866164842
Short name T1056
Test name
Test status
Simulation time 44912335 ps
CPU time 1.58 seconds
Started Jun 24 05:43:37 PM PDT 24
Finished Jun 24 05:43:45 PM PDT 24
Peak memory 214564 kb
Host smart-dbd7d2c6-e552-4a23-8eb5-e99dd6232c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866164842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.866164842
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3016645615
Short name T1108
Test name
Test status
Simulation time 20284851 ps
CPU time 1.14 seconds
Started Jun 24 05:43:55 PM PDT 24
Finished Jun 24 05:43:59 PM PDT 24
Peak memory 214700 kb
Host smart-d9cd7adf-be84-4696-ab63-6c0f5614c87c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016645615 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3016645615
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2061643717
Short name T1099
Test name
Test status
Simulation time 62403279 ps
CPU time 0.93 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206280 kb
Host smart-d8b18de3-e2e6-48d1-9704-2b67c1bed537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061643717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2061643717
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.505144466
Short name T1089
Test name
Test status
Simulation time 17847207 ps
CPU time 0.98 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:43 PM PDT 24
Peak memory 206112 kb
Host smart-20ba32f6-6516-4132-9dd2-c28bdf2bcda9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505144466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.505144466
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2194848267
Short name T1083
Test name
Test status
Simulation time 70121900 ps
CPU time 1.49 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206376 kb
Host smart-46d36b75-5fc8-4fea-9101-5acb3ccb09d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194848267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2194848267
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1021380454
Short name T1044
Test name
Test status
Simulation time 323995949 ps
CPU time 1.85 seconds
Started Jun 24 05:43:43 PM PDT 24
Finished Jun 24 05:43:46 PM PDT 24
Peak memory 214708 kb
Host smart-8a9c91a2-71d3-4d57-9d14-8668e2d07b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021380454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1021380454
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.268534912
Short name T290
Test name
Test status
Simulation time 44991426 ps
CPU time 1.69 seconds
Started Jun 24 05:43:41 PM PDT 24
Finished Jun 24 05:43:44 PM PDT 24
Peak memory 206168 kb
Host smart-7715cbfd-66c1-44d2-b8b9-d2c8fbb4865e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268534912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.268534912
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1289234036
Short name T1039
Test name
Test status
Simulation time 20156125 ps
CPU time 1.29 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:47 PM PDT 24
Peak memory 214548 kb
Host smart-3cea0304-267e-4fed-a478-bbdd6b72b682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289234036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1289234036
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2838617891
Short name T1041
Test name
Test status
Simulation time 68451629 ps
CPU time 0.87 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206308 kb
Host smart-ed0f3b40-4e6f-46ad-9ee8-8e42ec19a816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838617891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2838617891
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3254257637
Short name T1008
Test name
Test status
Simulation time 16420709 ps
CPU time 0.87 seconds
Started Jun 24 05:43:44 PM PDT 24
Finished Jun 24 05:43:47 PM PDT 24
Peak memory 206244 kb
Host smart-90062081-d4fe-4fec-adb6-a8e334115349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254257637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3254257637
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3802416371
Short name T1097
Test name
Test status
Simulation time 30393144 ps
CPU time 1.15 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206352 kb
Host smart-ad078a2e-475b-4ab6-ab00-14f60539d40b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802416371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3802416371
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2121337030
Short name T1026
Test name
Test status
Simulation time 122969249 ps
CPU time 2.43 seconds
Started Jun 24 05:43:46 PM PDT 24
Finished Jun 24 05:43:51 PM PDT 24
Peak memory 214648 kb
Host smart-3190ced2-1a81-42d3-b6e4-8e84452ffb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121337030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2121337030
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2070326280
Short name T1061
Test name
Test status
Simulation time 152040651 ps
CPU time 2.2 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206532 kb
Host smart-8a765622-9cd5-420d-866e-91955361c808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070326280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2070326280
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2131323307
Short name T1093
Test name
Test status
Simulation time 37028039 ps
CPU time 1.61 seconds
Started Jun 24 05:44:06 PM PDT 24
Finished Jun 24 05:44:09 PM PDT 24
Peak memory 214764 kb
Host smart-d0973845-2b8b-49d8-951b-ad1ff0910dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131323307 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2131323307
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2612074946
Short name T278
Test name
Test status
Simulation time 16301556 ps
CPU time 0.84 seconds
Started Jun 24 05:43:50 PM PDT 24
Finished Jun 24 05:43:55 PM PDT 24
Peak memory 206256 kb
Host smart-f3d65690-02ab-47df-bbe1-e7de5f6b275d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612074946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2612074946
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.994689150
Short name T1020
Test name
Test status
Simulation time 22733310 ps
CPU time 0.86 seconds
Started Jun 24 05:43:48 PM PDT 24
Finished Jun 24 05:43:53 PM PDT 24
Peak memory 206312 kb
Host smart-5d1b2948-23bd-45c3-a22f-57408f26e22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994689150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.994689150
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3207985940
Short name T1075
Test name
Test status
Simulation time 65058803 ps
CPU time 1.09 seconds
Started Jun 24 05:43:51 PM PDT 24
Finished Jun 24 05:43:56 PM PDT 24
Peak memory 206656 kb
Host smart-c11ae691-5f97-45ab-8c0e-122e42207a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207985940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3207985940
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2918274869
Short name T1019
Test name
Test status
Simulation time 22627938 ps
CPU time 1.5 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 214648 kb
Host smart-bc03f845-4f0e-4b26-96d6-f1e27cf2c63f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918274869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2918274869
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2233418202
Short name T1028
Test name
Test status
Simulation time 84473604 ps
CPU time 1.86 seconds
Started Jun 24 05:43:47 PM PDT 24
Finished Jun 24 05:43:52 PM PDT 24
Peak memory 206832 kb
Host smart-980beb40-54ab-4796-8b7f-0c2bae484a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233418202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2233418202
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.416889725
Short name T138
Test name
Test status
Simulation time 351681126 ps
CPU time 1.3 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:22 PM PDT 24
Peak memory 218000 kb
Host smart-2760621f-43e8-4347-b454-f2f77332bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416889725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.416889725
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.4062246082
Short name T867
Test name
Test status
Simulation time 26117757 ps
CPU time 1.07 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:22 PM PDT 24
Peak memory 206180 kb
Host smart-7d3983af-2e2e-4e07-b416-e3cff74056b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062246082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.4062246082
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3272432723
Short name T592
Test name
Test status
Simulation time 17288035 ps
CPU time 0.88 seconds
Started Jun 24 06:28:20 PM PDT 24
Finished Jun 24 06:28:22 PM PDT 24
Peak memory 215300 kb
Host smart-13608859-3f6e-4388-84ec-f5235437f429
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272432723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3272432723
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3270602062
Short name T759
Test name
Test status
Simulation time 27753752 ps
CPU time 1.06 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:28:20 PM PDT 24
Peak memory 217704 kb
Host smart-8b769230-0ff7-40d1-a1e6-0863a392eaeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270602062 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3270602062
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.1385218100
Short name T571
Test name
Test status
Simulation time 162912722 ps
CPU time 1.13 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:28:20 PM PDT 24
Peak memory 216680 kb
Host smart-9f4599b8-6182-4f09-985a-7f61a62b5a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385218100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1385218100
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.166342192
Short name T30
Test name
Test status
Simulation time 28544435 ps
CPU time 0.86 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:21 PM PDT 24
Peak memory 215064 kb
Host smart-21e985e5-dcf0-4f9a-a003-358b22ceaaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166342192 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.166342192
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2387274207
Short name T920
Test name
Test status
Simulation time 50388969 ps
CPU time 0.96 seconds
Started Jun 24 06:28:19 PM PDT 24
Finished Jun 24 06:28:22 PM PDT 24
Peak memory 206424 kb
Host smart-4524b02f-7433-4ef1-9ea6-48fc3fad359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387274207 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2387274207
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2358440020
Short name T694
Test name
Test status
Simulation time 40647858 ps
CPU time 0.94 seconds
Started Jun 24 06:28:17 PM PDT 24
Finished Jun 24 06:28:19 PM PDT 24
Peak memory 214624 kb
Host smart-be0c4c5a-bb36-471f-8144-2f08ee4c50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358440020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2358440020
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.946080370
Short name T667
Test name
Test status
Simulation time 1675851241 ps
CPU time 4.3 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:28:23 PM PDT 24
Peak memory 214572 kb
Host smart-4ba5b816-3586-4482-bb92-25971cb97a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946080370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.946080370
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2523635840
Short name T246
Test name
Test status
Simulation time 16239184825 ps
CPU time 354.56 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:34:14 PM PDT 24
Peak memory 216804 kb
Host smart-aaec6432-dbcb-4b41-abbe-70ad946500d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523635840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2523635840
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1980647333
Short name T386
Test name
Test status
Simulation time 28786587 ps
CPU time 1.21 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 219256 kb
Host smart-b8dec612-f666-434d-a814-9cbdae9d77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980647333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1980647333
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.3964365756
Short name T223
Test name
Test status
Simulation time 21907670 ps
CPU time 0.9 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 215656 kb
Host smart-46fe59f5-63be-433a-9c96-c15021277097
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964365756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3964365756
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1813147602
Short name T162
Test name
Test status
Simulation time 75408637 ps
CPU time 1.04 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 216188 kb
Host smart-1c2babba-8c19-4f28-a334-682dfae43b7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813147602 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1813147602
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2482950164
Short name T942
Test name
Test status
Simulation time 45624749 ps
CPU time 1.1 seconds
Started Jun 24 06:28:28 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 218940 kb
Host smart-136d1507-86e8-463e-9780-babde4208f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482950164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2482950164
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3183128257
Short name T108
Test name
Test status
Simulation time 114314258 ps
CPU time 2.31 seconds
Started Jun 24 06:28:18 PM PDT 24
Finished Jun 24 06:28:21 PM PDT 24
Peak memory 214648 kb
Host smart-3e3b2dd5-7757-4a0f-aea2-a46aa4baffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183128257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3183128257
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1973240920
Short name T950
Test name
Test status
Simulation time 25093635 ps
CPU time 1.04 seconds
Started Jun 24 06:28:16 PM PDT 24
Finished Jun 24 06:28:18 PM PDT 24
Peak memory 223388 kb
Host smart-3c4acbcd-584d-49ad-b301-45f696baf61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973240920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1973240920
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.436494681
Short name T17
Test name
Test status
Simulation time 870273843 ps
CPU time 4.31 seconds
Started Jun 24 06:28:24 PM PDT 24
Finished Jun 24 06:28:29 PM PDT 24
Peak memory 234908 kb
Host smart-1db11728-d46b-4e8f-b370-a3505504ae9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436494681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.436494681
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2203347901
Short name T467
Test name
Test status
Simulation time 73036744 ps
CPU time 0.9 seconds
Started Jun 24 06:28:17 PM PDT 24
Finished Jun 24 06:28:18 PM PDT 24
Peak memory 214644 kb
Host smart-939fbd8b-13f3-4c76-952e-6297eee3a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203347901 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2203347901
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_alert_test.275175421
Short name T433
Test name
Test status
Simulation time 95914671 ps
CPU time 1 seconds
Started Jun 24 06:28:55 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 206208 kb
Host smart-9204e7db-def1-488d-b5bd-bfa589b6fae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275175421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.275175421
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3205525410
Short name T747
Test name
Test status
Simulation time 42112665 ps
CPU time 1.12 seconds
Started Jun 24 06:28:57 PM PDT 24
Finished Jun 24 06:28:58 PM PDT 24
Peak memory 216560 kb
Host smart-face73b4-ad8f-4c20-bc79-dd16f0ffc997
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205525410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3205525410
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3817598166
Short name T561
Test name
Test status
Simulation time 29810182 ps
CPU time 0.97 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 223196 kb
Host smart-b1acfd6d-a62f-48fa-a5eb-40f03d1f970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817598166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3817598166
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2177487362
Short name T508
Test name
Test status
Simulation time 78910930 ps
CPU time 2.05 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 219596 kb
Host smart-d32ab5da-4cc8-45b3-902c-df468d71df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177487362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2177487362
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1997954967
Short name T617
Test name
Test status
Simulation time 85133006 ps
CPU time 0.89 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:55 PM PDT 24
Peak memory 214624 kb
Host smart-518bd7cf-1cbd-4874-8e5e-95c6bc4914de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997954967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1997954967
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.815118518
Short name T970
Test name
Test status
Simulation time 363236641 ps
CPU time 7.23 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 214640 kb
Host smart-04d97f00-3ccd-4065-9672-2beb2ae39f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815118518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.815118518
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.686650710
Short name T244
Test name
Test status
Simulation time 156052705565 ps
CPU time 1639.16 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:56:24 PM PDT 24
Peak memory 224160 kb
Host smart-0db78ed3-1b19-41d1-9ef0-e5bd6430a401
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686650710 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.686650710
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_alert.3961315281
Short name T581
Test name
Test status
Simulation time 50347150 ps
CPU time 1.3 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 220480 kb
Host smart-1903c46d-36ea-4e01-b2fa-b14086989c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961315281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3961315281
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.390162207
Short name T522
Test name
Test status
Simulation time 333465293 ps
CPU time 1.26 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 216624 kb
Host smart-dfc2fc72-7bbc-4539-94e2-0933571d7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390162207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.390162207
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_alert.219394601
Short name T172
Test name
Test status
Simulation time 422000813 ps
CPU time 1.49 seconds
Started Jun 24 06:31:21 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 219488 kb
Host smart-989aa146-c750-42e2-b674-ff53615764dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219394601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.219394601
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/102.edn_alert.2450447007
Short name T233
Test name
Test status
Simulation time 81048154 ps
CPU time 1.21 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 218284 kb
Host smart-f9e89200-9f7b-477b-b0d4-7ab5c1f0e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450447007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2450447007
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.2296042012
Short name T814
Test name
Test status
Simulation time 57122650 ps
CPU time 1.5 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 217960 kb
Host smart-856709d0-b099-4b56-b9fd-36a33f276cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296042012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2296042012
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_alert.3857232616
Short name T907
Test name
Test status
Simulation time 25485264 ps
CPU time 1.23 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 218080 kb
Host smart-9fcf8199-e661-483a-b0c8-2fb783a1263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857232616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3857232616
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.1700725073
Short name T502
Test name
Test status
Simulation time 142302689 ps
CPU time 1.1 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 216576 kb
Host smart-eba4a56f-1fc5-4914-a2d3-bea5853dec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700725073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1700725073
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1589477076
Short name T844
Test name
Test status
Simulation time 66676459 ps
CPU time 1.09 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 217968 kb
Host smart-00148fef-43a9-4a2f-8d87-13186b62efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589477076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1589477076
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3655601578
Short name T564
Test name
Test status
Simulation time 89601124 ps
CPU time 1.33 seconds
Started Jun 24 06:31:17 PM PDT 24
Finished Jun 24 06:31:20 PM PDT 24
Peak memory 216568 kb
Host smart-5ee06a87-1648-4284-a6ec-07627bf2b599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655601578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3655601578
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.3996858486
Short name T185
Test name
Test status
Simulation time 74794731 ps
CPU time 1.11 seconds
Started Jun 24 06:31:22 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 218200 kb
Host smart-864e1789-67c7-451f-a825-b6d0edec017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996858486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.3996858486
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.2605427549
Short name T540
Test name
Test status
Simulation time 44808833 ps
CPU time 1.99 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 217976 kb
Host smart-5fc7d440-44f6-4a4d-be24-cab61e1452b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605427549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2605427549
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_alert.3895295736
Short name T754
Test name
Test status
Simulation time 44998287 ps
CPU time 1.14 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 220172 kb
Host smart-5f7b8a22-32d0-4fda-9826-9c3e8fccdf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895295736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.3895295736
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/109.edn_alert.86522384
Short name T546
Test name
Test status
Simulation time 31555177 ps
CPU time 1.36 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:21 PM PDT 24
Peak memory 215092 kb
Host smart-8ebeb8a0-1fb5-401b-9b61-16b125bfbaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86522384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.86522384
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.522676181
Short name T961
Test name
Test status
Simulation time 64010286 ps
CPU time 1.33 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 216508 kb
Host smart-9adea47f-de28-4bd3-8e89-afbf1727740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522676181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.522676181
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1547156287
Short name T186
Test name
Test status
Simulation time 43535264 ps
CPU time 1.13 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 215072 kb
Host smart-0bd51a87-4229-40ba-9f39-906efef14f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547156287 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1547156287
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3828946582
Short name T902
Test name
Test status
Simulation time 71862329 ps
CPU time 0.94 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 214580 kb
Host smart-c55a2ea1-cc85-4bb0-b4e4-5d50c39ea374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828946582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3828946582
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1034454506
Short name T136
Test name
Test status
Simulation time 93245307 ps
CPU time 1.16 seconds
Started Jun 24 06:29:00 PM PDT 24
Finished Jun 24 06:29:02 PM PDT 24
Peak memory 216188 kb
Host smart-e7fde712-899f-4475-a769-587b84795079
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034454506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1034454506
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.2636838407
Short name T348
Test name
Test status
Simulation time 60194086 ps
CPU time 1.12 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 217992 kb
Host smart-9930c1b4-c14b-4d87-85f3-28fb98efa75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636838407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2636838407
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.3390385765
Short name T716
Test name
Test status
Simulation time 25032952 ps
CPU time 0.93 seconds
Started Jun 24 06:28:52 PM PDT 24
Finished Jun 24 06:28:53 PM PDT 24
Peak memory 214584 kb
Host smart-d188781e-fed0-4c40-9538-eec8b168a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390385765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3390385765
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1803770983
Short name T341
Test name
Test status
Simulation time 140140398 ps
CPU time 3 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 219484 kb
Host smart-ae0bb577-db21-4f95-a9fc-4b851a79485c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803770983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1803770983
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3339132679
Short name T940
Test name
Test status
Simulation time 17188318726 ps
CPU time 396 seconds
Started Jun 24 06:28:55 PM PDT 24
Finished Jun 24 06:35:32 PM PDT 24
Peak memory 220680 kb
Host smart-c826ca9b-126b-4e43-815f-07ae34a3e208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339132679 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3339132679
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1771084980
Short name T838
Test name
Test status
Simulation time 29784237 ps
CPU time 1.3 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 220028 kb
Host smart-c8f61527-a370-446f-b488-9580074fbaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771084980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1771084980
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.2021664831
Short name T682
Test name
Test status
Simulation time 31057319 ps
CPU time 1.41 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 219320 kb
Host smart-0a502190-a2ce-4c66-bc25-8275a79f65ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021664831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2021664831
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1494962324
Short name T709
Test name
Test status
Simulation time 30219135 ps
CPU time 1.26 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 217904 kb
Host smart-49a615a9-768c-4c8c-aa69-a2adbf7b0a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494962324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1494962324
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.2086618024
Short name T536
Test name
Test status
Simulation time 70985936 ps
CPU time 1.1 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 216732 kb
Host smart-b029c33f-f90a-491c-bee1-6e8bbe4070db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086618024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2086618024
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3656140837
Short name T837
Test name
Test status
Simulation time 91376627 ps
CPU time 1.27 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 219112 kb
Host smart-3e579545-1c97-4211-9e03-59abe85dde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656140837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3656140837
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1860985877
Short name T827
Test name
Test status
Simulation time 76950783 ps
CPU time 2.73 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 216796 kb
Host smart-b05f70c7-dd2e-4a60-98de-a44410a89d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860985877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1860985877
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3816274573
Short name T501
Test name
Test status
Simulation time 56872958 ps
CPU time 1.12 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 216592 kb
Host smart-4b2c8345-2454-4105-9f30-5c48bb494318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816274573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3816274573
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1621493931
Short name T311
Test name
Test status
Simulation time 73732113 ps
CPU time 1.1 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 219420 kb
Host smart-41ea0b61-bf16-4435-98cb-5fa2b1424534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621493931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1621493931
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3998392770
Short name T980
Test name
Test status
Simulation time 93171981 ps
CPU time 1.87 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 218284 kb
Host smart-ea0afd6b-7956-4685-8974-0a4c0786892e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998392770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3998392770
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.3399590923
Short name T10
Test name
Test status
Simulation time 51844179 ps
CPU time 1.25 seconds
Started Jun 24 06:31:22 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 219144 kb
Host smart-393d3e9a-6a6d-4b9e-85e7-3b3634310fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399590923 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.3399590923
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.1643867757
Short name T976
Test name
Test status
Simulation time 116731177 ps
CPU time 1.22 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:23 PM PDT 24
Peak memory 218544 kb
Host smart-cb358004-39ac-4534-bd60-ed0e1f18a034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643867757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1643867757
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1247659607
Short name T931
Test name
Test status
Simulation time 81637524 ps
CPU time 1.13 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 218648 kb
Host smart-1f910856-ed29-4949-a259-dd6fa7037250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247659607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1247659607
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.3084687904
Short name T905
Test name
Test status
Simulation time 61127102 ps
CPU time 1.58 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 217988 kb
Host smart-62079570-8f21-4d85-b0d5-c458f3ab7de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084687904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3084687904
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.2408134267
Short name T969
Test name
Test status
Simulation time 29401794 ps
CPU time 1.26 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 219044 kb
Host smart-0325bbd2-0ac8-4d8e-87c1-5a8604838e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408134267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.2408134267
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2698489983
Short name T510
Test name
Test status
Simulation time 138973766 ps
CPU time 1.22 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 216748 kb
Host smart-fa1ccfa7-cb43-4033-b7e3-218f4a26694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698489983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2698489983
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.1968739702
Short name T587
Test name
Test status
Simulation time 214049815 ps
CPU time 1.13 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:20 PM PDT 24
Peak memory 219112 kb
Host smart-1ddba6f3-9c83-4850-b9c1-b624b6a32c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968739702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.1968739702
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.2051082979
Short name T444
Test name
Test status
Simulation time 61214668 ps
CPU time 1.57 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 216980 kb
Host smart-f58a905d-4dbd-4764-9b3f-244c6de17bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051082979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2051082979
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3224336402
Short name T579
Test name
Test status
Simulation time 130568689 ps
CPU time 1.19 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:13 PM PDT 24
Peak memory 218148 kb
Host smart-245a4c92-80fd-42dc-b8e9-a87b6e1f0acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224336402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3224336402
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3856479505
Short name T895
Test name
Test status
Simulation time 40539389 ps
CPU time 0.88 seconds
Started Jun 24 06:29:05 PM PDT 24
Finished Jun 24 06:29:07 PM PDT 24
Peak memory 206060 kb
Host smart-db53dea2-a8d3-46e0-bda2-d555ee0093f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856479505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3856479505
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1580245568
Short name T979
Test name
Test status
Simulation time 126596084 ps
CPU time 1.3 seconds
Started Jun 24 06:28:59 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 216504 kb
Host smart-f4cd78f0-6cb8-443f-a0c8-f2786717bf94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580245568 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1580245568
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1694784278
Short name T4
Test name
Test status
Simulation time 56549762 ps
CPU time 0.81 seconds
Started Jun 24 06:28:59 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 217488 kb
Host smart-9199d42c-4675-485c-af4e-037cf6f8ab08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694784278 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1694784278
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2822992557
Short name T622
Test name
Test status
Simulation time 50696118 ps
CPU time 1.4 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 218164 kb
Host smart-828c304e-6816-404c-ac41-e9c1f5edb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822992557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2822992557
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2220805857
Short name T547
Test name
Test status
Simulation time 24722184 ps
CPU time 0.93 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 214648 kb
Host smart-44f816be-c457-45f4-8835-e054915a9267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220805857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2220805857
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3294247217
Short name T416
Test name
Test status
Simulation time 756783944 ps
CPU time 4.29 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 216740 kb
Host smart-acfe4440-45c5-4379-8ddc-69ec3b5cc984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294247217 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3294247217
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4087274436
Short name T853
Test name
Test status
Simulation time 282615757939 ps
CPU time 2112.38 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 07:04:16 PM PDT 24
Peak memory 225964 kb
Host smart-b920f084-21b7-47e6-8122-bfc04266dcab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087274436 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4087274436
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.2997029489
Short name T369
Test name
Test status
Simulation time 66712215 ps
CPU time 1.14 seconds
Started Jun 24 06:31:23 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 217864 kb
Host smart-3113d306-fc04-4aa1-a287-916c86bde1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997029489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.2997029489
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1740033345
Short name T320
Test name
Test status
Simulation time 144000023 ps
CPU time 2 seconds
Started Jun 24 06:31:19 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 219336 kb
Host smart-761d83c6-7082-4dcc-a9c2-487e0464ace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740033345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1740033345
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1701483464
Short name T805
Test name
Test status
Simulation time 246156875 ps
CPU time 1.33 seconds
Started Jun 24 06:31:21 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 220072 kb
Host smart-ee116fb2-78e7-4a00-bd8f-0dea9fdb7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701483464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1701483464
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2463616079
Short name T890
Test name
Test status
Simulation time 39286211 ps
CPU time 1.38 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:24 PM PDT 24
Peak memory 217652 kb
Host smart-1ff022e8-685c-47a4-864a-20ea69cdb0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463616079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2463616079
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.3195643651
Short name T173
Test name
Test status
Simulation time 35525543 ps
CPU time 1.13 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 218180 kb
Host smart-00fcf3f1-a9bd-4000-8f8d-6e445f7a56d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195643651 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.3195643651
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.157362463
Short name T881
Test name
Test status
Simulation time 56523291 ps
CPU time 2.15 seconds
Started Jun 24 06:31:20 PM PDT 24
Finished Jun 24 06:31:26 PM PDT 24
Peak memory 216820 kb
Host smart-01a44774-ce94-4b34-b4fa-41ff6e9d0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157362463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.157362463
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.951699440
Short name T630
Test name
Test status
Simulation time 86466489 ps
CPU time 1.21 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 219064 kb
Host smart-48b16ae3-f96e-411b-b3af-1b61b5ee450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951699440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.951699440
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.266994009
Short name T765
Test name
Test status
Simulation time 96743381 ps
CPU time 1.46 seconds
Started Jun 24 06:31:32 PM PDT 24
Finished Jun 24 06:31:35 PM PDT 24
Peak memory 217980 kb
Host smart-2f8b2256-66cf-48d5-9fc5-8c74f552e288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266994009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.266994009
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.4017220366
Short name T137
Test name
Test status
Simulation time 133057243 ps
CPU time 1.29 seconds
Started Jun 24 06:31:30 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 219100 kb
Host smart-8cba0d50-b4fc-49e1-aafe-3bd3bc6c25ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017220366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.4017220366
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.695156402
Short name T421
Test name
Test status
Simulation time 47463872 ps
CPU time 1.16 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 217896 kb
Host smart-07dbe3c4-e8ed-4232-9f28-7bb9863df332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695156402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.695156402
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2408103097
Short name T578
Test name
Test status
Simulation time 85550141 ps
CPU time 1.32 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 216588 kb
Host smart-9c141dd3-3073-4090-a815-3b6072892668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408103097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2408103097
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_alert.2339530319
Short name T89
Test name
Test status
Simulation time 55059190 ps
CPU time 1.27 seconds
Started Jun 24 06:31:32 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 219920 kb
Host smart-b4416926-c70c-4ef3-9c50-837e3ada6273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339530319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2339530319
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.999046662
Short name T669
Test name
Test status
Simulation time 80578442 ps
CPU time 1.16 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 216808 kb
Host smart-6706dbbd-7b78-4c75-bf62-b18c9875ccc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999046662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.999046662
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2417894872
Short name T165
Test name
Test status
Simulation time 27644143 ps
CPU time 1.25 seconds
Started Jun 24 06:31:35 PM PDT 24
Finished Jun 24 06:31:37 PM PDT 24
Peak memory 219736 kb
Host smart-683abd27-9f08-4e22-9b3a-22b3cbf88096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417894872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2417894872
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3970219853
Short name T393
Test name
Test status
Simulation time 39286642 ps
CPU time 1.24 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 216560 kb
Host smart-743e4804-22da-4554-9423-5a4d0c4513dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970219853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3970219853
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.4033619285
Short name T609
Test name
Test status
Simulation time 30708463 ps
CPU time 1.49 seconds
Started Jun 24 06:31:32 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 217708 kb
Host smart-8de760a4-d9dd-4a5d-bd64-c3fe9e31240e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033619285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4033619285
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3343761296
Short name T326
Test name
Test status
Simulation time 58573333 ps
CPU time 1.32 seconds
Started Jun 24 06:31:26 PM PDT 24
Finished Jun 24 06:31:28 PM PDT 24
Peak memory 216496 kb
Host smart-1fed274e-a949-4ce9-a18a-67fcebac6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343761296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3343761296
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3788098587
Short name T51
Test name
Test status
Simulation time 106693081 ps
CPU time 1.31 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:03 PM PDT 24
Peak memory 215088 kb
Host smart-6648131d-2279-464f-a9cb-5100ea68d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788098587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3788098587
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.956208496
Short name T921
Test name
Test status
Simulation time 26888927 ps
CPU time 0.91 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 206096 kb
Host smart-2932519b-9104-4c39-8a8b-3a0e0906f70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956208496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.956208496
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.547068795
Short name T887
Test name
Test status
Simulation time 11634457 ps
CPU time 0.9 seconds
Started Jun 24 06:29:00 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 215660 kb
Host smart-00ab1020-e803-4345-9df8-7c80e595801b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547068795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.547068795
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.912870377
Short name T286
Test name
Test status
Simulation time 48109617 ps
CPU time 1.06 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 217500 kb
Host smart-d75f8bd5-f9fb-42ed-aad9-738f29d33c1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912870377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.912870377
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.426449083
Short name T799
Test name
Test status
Simulation time 18963697 ps
CPU time 1.08 seconds
Started Jun 24 06:29:05 PM PDT 24
Finished Jun 24 06:29:07 PM PDT 24
Peak memory 217712 kb
Host smart-65e2924d-8d91-4752-bcd0-4559bf76ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426449083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.426449083
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2124384
Short name T787
Test name
Test status
Simulation time 276687013 ps
CPU time 1.37 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 219268 kb
Host smart-fcc9fccc-d4fc-44af-bd6c-f7de2507b947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2124384
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2642152175
Short name T888
Test name
Test status
Simulation time 38371533 ps
CPU time 1.06 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 223368 kb
Host smart-81c9de96-00ed-4899-b347-e172a767809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642152175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2642152175
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3673332687
Short name T820
Test name
Test status
Simulation time 51469155 ps
CPU time 0.96 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 214696 kb
Host smart-81936c60-23fd-4264-931b-065c7351cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673332687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3673332687
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4119085949
Short name T427
Test name
Test status
Simulation time 532495026 ps
CPU time 5.11 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:09 PM PDT 24
Peak memory 216388 kb
Host smart-b7c50de8-1e0d-4d63-97f7-57fa58010d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119085949 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4119085949
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2151785038
Short name T485
Test name
Test status
Simulation time 93738150002 ps
CPU time 1167.99 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:48:32 PM PDT 24
Peak memory 222992 kb
Host smart-af60d02d-aad1-4da5-ba83-a3256beb3fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151785038 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2151785038
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3770220933
Short name T712
Test name
Test status
Simulation time 63465551 ps
CPU time 1.28 seconds
Started Jun 24 06:31:30 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 218780 kb
Host smart-87dbf579-a0d8-4ddf-9286-7617dee548b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770220933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3770220933
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.201899519
Short name T506
Test name
Test status
Simulation time 182820918 ps
CPU time 1.32 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 217840 kb
Host smart-112d6320-bc9b-4473-a697-ca2526878695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201899519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.201899519
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.80889801
Short name T698
Test name
Test status
Simulation time 103321623 ps
CPU time 1.32 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 221064 kb
Host smart-665a549b-c948-4b2f-841d-0312032039ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80889801 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.80889801
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3784200596
Short name T342
Test name
Test status
Simulation time 94631359 ps
CPU time 1.25 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 216772 kb
Host smart-9e7971db-47fd-400d-bec3-bc3d86c2bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784200596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3784200596
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.2139335901
Short name T130
Test name
Test status
Simulation time 220835062 ps
CPU time 1.37 seconds
Started Jun 24 06:31:30 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 219088 kb
Host smart-bdd1f0ae-992b-435d-9b3b-8fec65d77a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139335901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.2139335901
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.3208450612
Short name T648
Test name
Test status
Simulation time 46284530 ps
CPU time 1.58 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 217832 kb
Host smart-e555d9fe-3ce2-43bb-ba20-423f545002c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208450612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3208450612
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.631480768
Short name T779
Test name
Test status
Simulation time 33062395 ps
CPU time 1.14 seconds
Started Jun 24 06:31:33 PM PDT 24
Finished Jun 24 06:31:35 PM PDT 24
Peak memory 218280 kb
Host smart-44ae9766-8c94-4f53-b567-d665de2b87c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631480768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.631480768
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.1567172611
Short name T883
Test name
Test status
Simulation time 16456215 ps
CPU time 1 seconds
Started Jun 24 06:31:34 PM PDT 24
Finished Jun 24 06:31:36 PM PDT 24
Peak memory 216792 kb
Host smart-9190bb2e-7880-435b-a0e5-b162b1d95f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567172611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1567172611
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.2986183636
Short name T197
Test name
Test status
Simulation time 117980714 ps
CPU time 1.18 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 219788 kb
Host smart-37df7bf3-fe78-4433-9b97-3221308b862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986183636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.2986183636
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.2556984179
Short name T591
Test name
Test status
Simulation time 65462855 ps
CPU time 1.45 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 217884 kb
Host smart-9a1db3dd-c0b1-4ee5-84ce-cbc2414f04a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556984179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2556984179
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.3746901003
Short name T738
Test name
Test status
Simulation time 72898246 ps
CPU time 1.12 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 219124 kb
Host smart-525abc90-498f-45f6-92a4-f110cdb9bd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746901003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.3746901003
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2670750212
Short name T492
Test name
Test status
Simulation time 64307274 ps
CPU time 1.21 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 218124 kb
Host smart-36812af8-bf9b-4c73-af85-b63a44691869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670750212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2670750212
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.4128612905
Short name T439
Test name
Test status
Simulation time 42825290 ps
CPU time 1.18 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 218032 kb
Host smart-36fde1e6-d572-4ec8-a624-b180d1c6a577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128612905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.4128612905
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.1921961819
Short name T323
Test name
Test status
Simulation time 143927265 ps
CPU time 3.26 seconds
Started Jun 24 06:31:35 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 217896 kb
Host smart-4df8a22e-1505-4f00-92bd-735434ee7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921961819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1921961819
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.1404991389
Short name T529
Test name
Test status
Simulation time 22204042 ps
CPU time 1.2 seconds
Started Jun 24 06:31:32 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 215068 kb
Host smart-aeec1f17-1f7f-4f17-ae1c-413dfc08148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404991389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.1404991389
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.247081802
Short name T673
Test name
Test status
Simulation time 69152961 ps
CPU time 1.42 seconds
Started Jun 24 06:31:33 PM PDT 24
Finished Jun 24 06:31:35 PM PDT 24
Peak memory 217988 kb
Host smart-096b8e1d-120b-4efe-b1e9-1adc81f06e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247081802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.247081802
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.155739840
Short name T645
Test name
Test status
Simulation time 26849601 ps
CPU time 1.16 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 219152 kb
Host smart-e0d4ef63-6708-4db5-90bd-e22dcb8be546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155739840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.155739840
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3214573105
Short name T314
Test name
Test status
Simulation time 94153145 ps
CPU time 1.28 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 218540 kb
Host smart-828fdfc4-1082-4a20-9335-fc20b0599a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214573105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3214573105
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2243614248
Short name T914
Test name
Test status
Simulation time 142430847 ps
CPU time 1.27 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 219160 kb
Host smart-444416a0-f68f-4816-8482-35ac2976b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243614248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2243614248
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3436058776
Short name T537
Test name
Test status
Simulation time 86874023 ps
CPU time 0.92 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 206104 kb
Host smart-6ec6af9d-6c0f-43ca-baea-5ae486e3d612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436058776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3436058776
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3236123135
Short name T615
Test name
Test status
Simulation time 39585222 ps
CPU time 0.88 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 215816 kb
Host smart-906b91e5-bbe7-49ee-82c6-2ea1019f995c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236123135 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3236123135
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.926226297
Short name T722
Test name
Test status
Simulation time 26517540 ps
CPU time 1.14 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 228996 kb
Host smart-95578029-280d-49e9-bd21-09cd2e123122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926226297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.926226297
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.966075646
Short name T465
Test name
Test status
Simulation time 296446464 ps
CPU time 1.3 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 218256 kb
Host smart-8aa7003a-e88f-4a38-a8b1-370f642f0717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966075646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.966075646
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3634684663
Short name T802
Test name
Test status
Simulation time 21470427 ps
CPU time 1.16 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 214760 kb
Host smart-441d6010-7050-4714-b7f0-542d3ef94d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634684663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3634684663
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.580318760
Short name T972
Test name
Test status
Simulation time 52110203 ps
CPU time 0.98 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 214792 kb
Host smart-92eac19c-9d9c-4efb-8df6-47b6b3b5cf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580318760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.580318760
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1636883688
Short name T432
Test name
Test status
Simulation time 279819440 ps
CPU time 5.64 seconds
Started Jun 24 06:29:00 PM PDT 24
Finished Jun 24 06:29:07 PM PDT 24
Peak memory 216628 kb
Host smart-17283cdc-afbd-432b-8a2e-f325511040d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636883688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1636883688
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3943583209
Short name T911
Test name
Test status
Simulation time 122286703251 ps
CPU time 1748.06 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:58:12 PM PDT 24
Peak memory 224044 kb
Host smart-0f33a7ba-ffb0-4596-b44f-37beadfdb5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943583209 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3943583209
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.3503331074
Short name T644
Test name
Test status
Simulation time 33032756 ps
CPU time 1.38 seconds
Started Jun 24 06:31:36 PM PDT 24
Finished Jun 24 06:31:38 PM PDT 24
Peak memory 215092 kb
Host smart-dc6c2bba-d414-4a61-802a-a500cbe18aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503331074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.3503331074
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.820808922
Short name T420
Test name
Test status
Simulation time 277565852 ps
CPU time 1.29 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 216824 kb
Host smart-f5c18461-ac30-4e7e-98f0-0a468ead6b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820808922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.820808922
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.2652909367
Short name T526
Test name
Test status
Simulation time 23926359 ps
CPU time 1.17 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:33 PM PDT 24
Peak memory 217840 kb
Host smart-5cd45d12-04e8-4a80-9958-e411fed09dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652909367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.2652909367
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.3014528551
Short name T670
Test name
Test status
Simulation time 111215743 ps
CPU time 1.26 seconds
Started Jun 24 06:31:35 PM PDT 24
Finished Jun 24 06:31:37 PM PDT 24
Peak memory 216616 kb
Host smart-e8277a9a-1ea7-4411-95aa-08bfd873a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014528551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3014528551
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.1796452052
Short name T808
Test name
Test status
Simulation time 92935244 ps
CPU time 1.26 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 215084 kb
Host smart-01378c35-7702-45bf-ac32-6b33ee2949c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796452052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.1796452052
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1311098204
Short name T704
Test name
Test status
Simulation time 37638045 ps
CPU time 1.53 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 219180 kb
Host smart-b88bb924-43b6-4dc8-8a3b-8141cc6efbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311098204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1311098204
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.2068318442
Short name T513
Test name
Test status
Simulation time 24104102 ps
CPU time 1.18 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:30 PM PDT 24
Peak memory 219128 kb
Host smart-ad87696f-96f7-4b19-b585-abdc0b5276fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068318442 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.2068318442
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.1366966456
Short name T60
Test name
Test status
Simulation time 76586188 ps
CPU time 1.03 seconds
Started Jun 24 06:31:33 PM PDT 24
Finished Jun 24 06:31:35 PM PDT 24
Peak memory 216520 kb
Host smart-633f047b-a2c1-4dd8-bfd6-6f24a11572b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366966456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1366966456
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.3302840749
Short name T394
Test name
Test status
Simulation time 93999225 ps
CPU time 1.23 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:30 PM PDT 24
Peak memory 219048 kb
Host smart-26d05753-6d30-4e08-a76f-40fff777d469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302840749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.3302840749
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.1430013577
Short name T830
Test name
Test status
Simulation time 23302204 ps
CPU time 1.11 seconds
Started Jun 24 06:31:35 PM PDT 24
Finished Jun 24 06:31:37 PM PDT 24
Peak memory 216696 kb
Host smart-530782c6-be1d-43ae-9344-3d215182135b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430013577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1430013577
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.3243254230
Short name T25
Test name
Test status
Simulation time 99321403 ps
CPU time 1.23 seconds
Started Jun 24 06:31:33 PM PDT 24
Finished Jun 24 06:31:36 PM PDT 24
Peak memory 219532 kb
Host smart-9d19ea01-bb00-48db-8a84-0c4fdb617b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243254230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.3243254230
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.186108269
Short name T742
Test name
Test status
Simulation time 110504640 ps
CPU time 1.25 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 216524 kb
Host smart-b5fa05a6-bbc3-4379-8e95-b387e28361cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186108269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.186108269
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.3257195227
Short name T461
Test name
Test status
Simulation time 47604053 ps
CPU time 1.36 seconds
Started Jun 24 06:31:29 PM PDT 24
Finished Jun 24 06:31:32 PM PDT 24
Peak memory 218252 kb
Host smart-bca83232-086b-47f1-97ae-7571cad04b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257195227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.3257195227
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2867582655
Short name T954
Test name
Test status
Simulation time 94142866 ps
CPU time 3.04 seconds
Started Jun 24 06:31:28 PM PDT 24
Finished Jun 24 06:31:31 PM PDT 24
Peak memory 217908 kb
Host smart-077350e4-340f-487c-81b5-718e759091ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867582655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2867582655
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.3879633271
Short name T494
Test name
Test status
Simulation time 30729581 ps
CPU time 1.34 seconds
Started Jun 24 06:31:32 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 219148 kb
Host smart-13bbdb69-e657-43c6-aa6b-bbe6a33615b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879633271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.3879633271
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3073995651
Short name T834
Test name
Test status
Simulation time 45766443 ps
CPU time 1.32 seconds
Started Jun 24 06:31:31 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 216792 kb
Host smart-c36f9d34-e01b-40ea-a9a8-7f020d18a2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073995651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3073995651
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.701956425
Short name T831
Test name
Test status
Simulation time 33405819 ps
CPU time 1.38 seconds
Started Jun 24 06:31:40 PM PDT 24
Finished Jun 24 06:31:42 PM PDT 24
Peak memory 215076 kb
Host smart-bdd5d54f-2d64-4f9d-a111-af4c8ff909a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701956425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.701956425
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.4207754116
Short name T811
Test name
Test status
Simulation time 66296391 ps
CPU time 1.26 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 216660 kb
Host smart-8e5dcee4-a55d-49b0-8835-5003153e759e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207754116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4207754116
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2396193211
Short name T66
Test name
Test status
Simulation time 92490897 ps
CPU time 1.21 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 217840 kb
Host smart-d757d27d-ef49-4b9f-9b7f-a66e23470e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396193211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2396193211
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3197793795
Short name T910
Test name
Test status
Simulation time 86476537 ps
CPU time 1.11 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 216544 kb
Host smart-bfd2523b-5b95-4ad3-b0d1-051f88b0f49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197793795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3197793795
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2268283491
Short name T971
Test name
Test status
Simulation time 81854643 ps
CPU time 1.18 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 220108 kb
Host smart-b2734e1b-791f-4e18-bf65-8030c5a9ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268283491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2268283491
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3990193904
Short name T365
Test name
Test status
Simulation time 45109396 ps
CPU time 0.92 seconds
Started Jun 24 06:29:12 PM PDT 24
Finished Jun 24 06:29:14 PM PDT 24
Peak memory 206168 kb
Host smart-335a052a-cc76-4f79-8a80-9537e298750f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990193904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3990193904
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2210156503
Short name T744
Test name
Test status
Simulation time 33239530 ps
CPU time 0.83 seconds
Started Jun 24 06:29:14 PM PDT 24
Finished Jun 24 06:29:15 PM PDT 24
Peak memory 215848 kb
Host smart-d67665fe-d708-461c-99c9-25266cd16b59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210156503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2210156503
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2885970623
Short name T736
Test name
Test status
Simulation time 113335842 ps
CPU time 1.01 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 219064 kb
Host smart-4a68adfa-7597-491b-99a5-ac39a390bc64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885970623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2885970623
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.76307261
Short name T208
Test name
Test status
Simulation time 20071993 ps
CPU time 1.07 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 218692 kb
Host smart-5a4a7da8-a605-4f30-938f-cd2ae52be167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76307261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.76307261
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2245600844
Short name T989
Test name
Test status
Simulation time 91006242 ps
CPU time 1.18 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 216728 kb
Host smart-9bae267c-6473-4590-b18b-e1345e609330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245600844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2245600844
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2055691136
Short name T112
Test name
Test status
Simulation time 36785864 ps
CPU time 0.83 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 214864 kb
Host smart-bbdb10c2-ed59-4e9d-85b2-240a655220db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055691136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2055691136
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2617434944
Short name T403
Test name
Test status
Simulation time 26224950 ps
CPU time 0.9 seconds
Started Jun 24 06:29:02 PM PDT 24
Finished Jun 24 06:29:05 PM PDT 24
Peak memory 214620 kb
Host smart-f8275933-a8ab-4ea1-8135-20964e9e3215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617434944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2617434944
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1477486381
Short name T733
Test name
Test status
Simulation time 278462519 ps
CPU time 5.68 seconds
Started Jun 24 06:29:05 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 218816 kb
Host smart-e897c0d9-e75b-494e-baca-e3fc83d64405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477486381 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1477486381
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3076741
Short name T845
Test name
Test status
Simulation time 68056812285 ps
CPU time 768.02 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:41:50 PM PDT 24
Peak memory 222868 kb
Host smart-dd5fc90f-0c55-467a-b13f-3076c20f5512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076741 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3076741
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1620528189
Short name T499
Test name
Test status
Simulation time 47148926 ps
CPU time 1.18 seconds
Started Jun 24 06:31:36 PM PDT 24
Finished Jun 24 06:31:38 PM PDT 24
Peak memory 219860 kb
Host smart-9165dbcb-65fa-4942-a680-dd75c07dbd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620528189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1620528189
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.140584154
Short name T98
Test name
Test status
Simulation time 105733175 ps
CPU time 1.59 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:40 PM PDT 24
Peak memory 218228 kb
Host smart-fe8cc52a-a1be-433e-b118-6f9120f99979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140584154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.140584154
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3817758377
Short name T761
Test name
Test status
Simulation time 51670383 ps
CPU time 1.16 seconds
Started Jun 24 06:31:40 PM PDT 24
Finished Jun 24 06:31:42 PM PDT 24
Peak memory 215064 kb
Host smart-3e1d6796-2753-4246-af9a-1c3200871578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817758377 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3817758377
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/152.edn_alert.3245044873
Short name T442
Test name
Test status
Simulation time 87694104 ps
CPU time 1.23 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:44 PM PDT 24
Peak memory 219424 kb
Host smart-8993f710-efbc-47dc-aa34-5d6002aa3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245044873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3245044873
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.142729813
Short name T71
Test name
Test status
Simulation time 96493015 ps
CPU time 1.05 seconds
Started Jun 24 06:31:52 PM PDT 24
Finished Jun 24 06:31:54 PM PDT 24
Peak memory 216724 kb
Host smart-5380dc64-7b2e-4f36-871b-6e42f91c11a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142729813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.142729813
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1133330257
Short name T234
Test name
Test status
Simulation time 30309086 ps
CPU time 1.37 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 215092 kb
Host smart-1b8df778-5b9f-498d-bfa9-b5eea19c9083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133330257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1133330257
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.19538775
Short name T869
Test name
Test status
Simulation time 170278264 ps
CPU time 1.54 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:42 PM PDT 24
Peak memory 218544 kb
Host smart-2786ae25-3397-416b-8bd6-ac406a623084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19538775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.19538775
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.749922672
Short name T983
Test name
Test status
Simulation time 93340426 ps
CPU time 1.27 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 219504 kb
Host smart-f0e019f7-bc16-4898-ae87-e4c34b7377bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749922672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.749922672
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.2685484630
Short name T43
Test name
Test status
Simulation time 67872066 ps
CPU time 1.63 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:44 PM PDT 24
Peak memory 217960 kb
Host smart-b8e21739-7799-47a9-8262-8f7b338d6e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685484630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2685484630
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2486656398
Short name T39
Test name
Test status
Simulation time 75436750 ps
CPU time 1.05 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 217888 kb
Host smart-91dc7491-53b2-42c2-817e-b42c4a203e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486656398 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2486656398
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2329796632
Short name T686
Test name
Test status
Simulation time 45504540 ps
CPU time 1.31 seconds
Started Jun 24 06:31:36 PM PDT 24
Finished Jun 24 06:31:38 PM PDT 24
Peak memory 216592 kb
Host smart-911ec798-1db4-4e31-87e3-a8a9734ff1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329796632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2329796632
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.1209922315
Short name T735
Test name
Test status
Simulation time 38047511 ps
CPU time 1.15 seconds
Started Jun 24 06:31:39 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 219556 kb
Host smart-2a779d4f-98eb-4218-821b-24e53961fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209922315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.1209922315
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.1815663923
Short name T681
Test name
Test status
Simulation time 299356754 ps
CPU time 4.31 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 218392 kb
Host smart-da1361be-7213-440a-89f5-903c1eaa7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815663923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1815663923
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1365599030
Short name T656
Test name
Test status
Simulation time 56386876 ps
CPU time 1.18 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 216732 kb
Host smart-a35b1d2d-06cf-467b-b710-be099c21d959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365599030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1365599030
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.1670789737
Short name T688
Test name
Test status
Simulation time 43523853 ps
CPU time 1.1 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 218224 kb
Host smart-0df94438-e5b7-45b7-b4ca-a7d25ea14083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670789737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.1670789737
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.2312122926
Short name T531
Test name
Test status
Simulation time 62599219 ps
CPU time 1.3 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 217724 kb
Host smart-f7036ea5-7b3b-443b-ab62-a5f203de781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312122926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2312122926
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.3357284065
Short name T823
Test name
Test status
Simulation time 38130227 ps
CPU time 1.24 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 219140 kb
Host smart-f57ed44a-175a-4466-9941-4f00fc3d790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357284065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.3357284065
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.2442420737
Short name T927
Test name
Test status
Simulation time 44169121 ps
CPU time 1.27 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:40 PM PDT 24
Peak memory 218268 kb
Host smart-31137e22-ccef-4a1b-a848-5ae272fa9afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442420737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2442420737
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.743335064
Short name T668
Test name
Test status
Simulation time 24766559 ps
CPU time 1.21 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 219100 kb
Host smart-3af31cf7-8b67-46d2-8616-0917963f32a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743335064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.743335064
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1260157869
Short name T851
Test name
Test status
Simulation time 21690273 ps
CPU time 1.08 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 206376 kb
Host smart-4abc06f0-be20-4753-b8ee-161273f556e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260157869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1260157869
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3213668674
Short name T101
Test name
Test status
Simulation time 49812967 ps
CPU time 0.83 seconds
Started Jun 24 06:29:08 PM PDT 24
Finished Jun 24 06:29:09 PM PDT 24
Peak memory 215812 kb
Host smart-b04e34cc-4486-4cf6-abfe-0fbca6f90050
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213668674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3213668674
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.97752690
Short name T768
Test name
Test status
Simulation time 44211644 ps
CPU time 1.36 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 216412 kb
Host smart-e027d9d9-e261-4df8-b5a8-411a13a1d829
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97752690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.97752690
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1786876562
Short name T126
Test name
Test status
Simulation time 68898889 ps
CPU time 0.95 seconds
Started Jun 24 06:29:12 PM PDT 24
Finished Jun 24 06:29:14 PM PDT 24
Peak memory 219108 kb
Host smart-20aa3dbd-16e6-43b0-b7fc-9aaa85dd8d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786876562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1786876562
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.4170080022
Short name T882
Test name
Test status
Simulation time 33850225 ps
CPU time 1.3 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 218792 kb
Host smart-8d25a94c-3f5f-45b7-bd6d-f9e8bfb1f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170080022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4170080022
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.971803897
Short name T932
Test name
Test status
Simulation time 25769320 ps
CPU time 0.97 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 214768 kb
Host smart-2a68bfd4-0e32-4406-a8d8-34b7c1e767f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971803897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.971803897
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2319200624
Short name T446
Test name
Test status
Simulation time 45029862 ps
CPU time 0.87 seconds
Started Jun 24 06:29:14 PM PDT 24
Finished Jun 24 06:29:16 PM PDT 24
Peak memory 214800 kb
Host smart-dbc6ca91-f976-4225-9145-6d58612ce6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319200624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2319200624
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.158948564
Short name T631
Test name
Test status
Simulation time 64607220 ps
CPU time 1.82 seconds
Started Jun 24 06:29:13 PM PDT 24
Finished Jun 24 06:29:15 PM PDT 24
Peak memory 214680 kb
Host smart-5e79d27e-b306-4285-9bce-fd2fb552d62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158948564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.158948564
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2421934903
Short name T74
Test name
Test status
Simulation time 37983907641 ps
CPU time 953.86 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:45:04 PM PDT 24
Peak memory 218456 kb
Host smart-3b71b3af-20bf-4a69-8bfb-a1e3821a9d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421934903 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2421934903
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.583605296
Short name T525
Test name
Test status
Simulation time 83630742 ps
CPU time 1.21 seconds
Started Jun 24 06:31:41 PM PDT 24
Finished Jun 24 06:31:43 PM PDT 24
Peak memory 219164 kb
Host smart-fe409c9d-95a8-4c39-8449-06679880423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583605296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.583605296
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1471492633
Short name T807
Test name
Test status
Simulation time 83749386 ps
CPU time 1.42 seconds
Started Jun 24 06:31:41 PM PDT 24
Finished Jun 24 06:31:43 PM PDT 24
Peak memory 218384 kb
Host smart-dafca4ac-dc94-4845-8977-efbf47513f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471492633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1471492633
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.1165566395
Short name T933
Test name
Test status
Simulation time 189228295 ps
CPU time 1.11 seconds
Started Jun 24 06:31:38 PM PDT 24
Finished Jun 24 06:31:40 PM PDT 24
Peak memory 220004 kb
Host smart-512650bf-2924-4a1f-8619-2c8fa78d9175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165566395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.1165566395
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3512998065
Short name T49
Test name
Test status
Simulation time 98596742 ps
CPU time 1.55 seconds
Started Jun 24 06:31:36 PM PDT 24
Finished Jun 24 06:31:38 PM PDT 24
Peak memory 218212 kb
Host smart-2e7caeec-264f-4419-b72b-e4777c3f5b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512998065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3512998065
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.172274453
Short name T919
Test name
Test status
Simulation time 46220317 ps
CPU time 1.21 seconds
Started Jun 24 06:31:41 PM PDT 24
Finished Jun 24 06:31:43 PM PDT 24
Peak memory 218368 kb
Host smart-7b79ac85-c296-4217-9774-81dd45fbe4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172274453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.172274453
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.2038119950
Short name T623
Test name
Test status
Simulation time 62708689 ps
CPU time 2.02 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:45 PM PDT 24
Peak memory 219224 kb
Host smart-5aefa699-ed2e-4560-94d0-1174833b8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038119950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2038119950
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.1861358931
Short name T939
Test name
Test status
Simulation time 52034909 ps
CPU time 1.21 seconds
Started Jun 24 06:31:40 PM PDT 24
Finished Jun 24 06:31:42 PM PDT 24
Peak memory 219184 kb
Host smart-712b9a23-591b-4626-9daa-3a994fbfcb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861358931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.1861358931
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.2732065392
Short name T42
Test name
Test status
Simulation time 131739543 ps
CPU time 1.4 seconds
Started Jun 24 06:31:36 PM PDT 24
Finished Jun 24 06:31:38 PM PDT 24
Peak memory 218204 kb
Host smart-8ef2cf5f-d2df-46a2-bdd6-d57b1e4bfb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732065392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2732065392
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3933168999
Short name T925
Test name
Test status
Simulation time 68854495 ps
CPU time 1.15 seconds
Started Jun 24 06:31:40 PM PDT 24
Finished Jun 24 06:31:41 PM PDT 24
Peak memory 219180 kb
Host smart-902136fd-8077-4551-b6ba-153a086295fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933168999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3933168999
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.4189603938
Short name T918
Test name
Test status
Simulation time 42490647 ps
CPU time 1.09 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:44 PM PDT 24
Peak memory 217872 kb
Host smart-874c16eb-aca6-4d37-8e74-b774c0ed7dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189603938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4189603938
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.1961237444
Short name T828
Test name
Test status
Simulation time 131589262 ps
CPU time 1.23 seconds
Started Jun 24 06:31:37 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 215080 kb
Host smart-070b1bc4-afdb-4f38-8337-1c080db77293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961237444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.1961237444
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.4135732748
Short name T868
Test name
Test status
Simulation time 113776763 ps
CPU time 2.72 seconds
Started Jun 24 06:31:42 PM PDT 24
Finished Jun 24 06:31:46 PM PDT 24
Peak memory 216840 kb
Host smart-f44e95eb-3112-4e5b-bcdf-d68962ac1e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135732748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4135732748
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.2984625553
Short name T745
Test name
Test status
Simulation time 32066265 ps
CPU time 1.35 seconds
Started Jun 24 06:31:52 PM PDT 24
Finished Jun 24 06:31:54 PM PDT 24
Peak memory 219368 kb
Host smart-c6554747-0216-4525-9752-be03b1597413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984625553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.2984625553
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2338480980
Short name T377
Test name
Test status
Simulation time 48571727 ps
CPU time 1.67 seconds
Started Jun 24 06:31:47 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 218108 kb
Host smart-37921b5a-2e62-4dbe-8ebe-8dffbb429adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338480980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2338480980
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.269141083
Short name T711
Test name
Test status
Simulation time 25434848 ps
CPU time 1.2 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 219344 kb
Host smart-7012ec93-3f9a-4ed9-9c28-c9e03dc35cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269141083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.269141083
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.1487580692
Short name T652
Test name
Test status
Simulation time 25531733 ps
CPU time 1.25 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 216848 kb
Host smart-eeef8e84-c259-47e0-bcb3-34389713865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487580692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1487580692
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1600782547
Short name T52
Test name
Test status
Simulation time 32461683 ps
CPU time 1.26 seconds
Started Jun 24 06:31:53 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 219440 kb
Host smart-75340215-ba74-4670-ad21-9a28eb76d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600782547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1600782547
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.1900997371
Short name T597
Test name
Test status
Simulation time 30030040 ps
CPU time 1.42 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 217880 kb
Host smart-3737ce65-9e24-4819-b630-ad9a0eba0db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900997371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1900997371
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.456744030
Short name T776
Test name
Test status
Simulation time 48694338 ps
CPU time 1.13 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 220168 kb
Host smart-982217ba-c89e-4586-80f6-4c3217c58233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456744030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.456744030
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.1743847198
Short name T847
Test name
Test status
Simulation time 59009153 ps
CPU time 1.34 seconds
Started Jun 24 06:31:50 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 216832 kb
Host smart-f29eca8c-02de-4533-9d90-ed49ffd40d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743847198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1743847198
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.307040053
Short name T293
Test name
Test status
Simulation time 29350976 ps
CPU time 1.33 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 219216 kb
Host smart-f7a10fdc-82aa-438b-81bc-fcf494abf327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307040053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.307040053
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1452909867
Short name T717
Test name
Test status
Simulation time 15316014 ps
CPU time 0.97 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 214300 kb
Host smart-907997b7-cc38-48a8-9043-7de85d59fcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452909867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1452909867
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1784666983
Short name T691
Test name
Test status
Simulation time 21749306 ps
CPU time 0.86 seconds
Started Jun 24 06:29:08 PM PDT 24
Finished Jun 24 06:29:10 PM PDT 24
Peak memory 215320 kb
Host smart-7d0b8b75-0c4f-4a05-870e-1726e76d46f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784666983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1784666983
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.266499536
Short name T988
Test name
Test status
Simulation time 69265354 ps
CPU time 1.26 seconds
Started Jun 24 06:29:11 PM PDT 24
Finished Jun 24 06:29:13 PM PDT 24
Peak memory 216176 kb
Host smart-917ec778-8ac5-46f0-9af4-8a822f391300
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266499536 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.266499536
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.3806092616
Short name T188
Test name
Test status
Simulation time 23785511 ps
CPU time 1.06 seconds
Started Jun 24 06:29:09 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 223380 kb
Host smart-84ed6213-289f-4310-824c-558785ac0215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806092616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3806092616
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2056922738
Short name T903
Test name
Test status
Simulation time 68970971 ps
CPU time 1.64 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:13 PM PDT 24
Peak memory 217848 kb
Host smart-40412f7c-a8dc-4702-8594-53f9648f4d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056922738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2056922738
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4064960322
Short name T18
Test name
Test status
Simulation time 29335170 ps
CPU time 1.12 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:12 PM PDT 24
Peak memory 223372 kb
Host smart-3d8151ee-0c22-4582-a888-68bfa5b63554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064960322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4064960322
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2836355049
Short name T79
Test name
Test status
Simulation time 17626670 ps
CPU time 0.94 seconds
Started Jun 24 06:29:14 PM PDT 24
Finished Jun 24 06:29:16 PM PDT 24
Peak memory 214820 kb
Host smart-b2bceee4-5d98-4f72-b1b4-c7976b53b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836355049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2836355049
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.4033981310
Short name T67
Test name
Test status
Simulation time 66617826 ps
CPU time 1.93 seconds
Started Jun 24 06:29:10 PM PDT 24
Finished Jun 24 06:29:13 PM PDT 24
Peak memory 219328 kb
Host smart-452661d8-d28c-41ed-9a82-c83536bb6a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033981310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.4033981310
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3875270246
Short name T237
Test name
Test status
Simulation time 176993548320 ps
CPU time 664.53 seconds
Started Jun 24 06:29:11 PM PDT 24
Finished Jun 24 06:40:17 PM PDT 24
Peak memory 219408 kb
Host smart-205d1eb2-5fa0-4ab0-878b-ae3525668420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875270246 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3875270246
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1440597620
Short name T413
Test name
Test status
Simulation time 290852451 ps
CPU time 1.22 seconds
Started Jun 24 06:31:47 PM PDT 24
Finished Jun 24 06:31:48 PM PDT 24
Peak memory 217812 kb
Host smart-1a2f868f-f307-4b0c-ab2e-110100476828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440597620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1440597620
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.2721695002
Short name T351
Test name
Test status
Simulation time 44309710 ps
CPU time 1.02 seconds
Started Jun 24 06:31:50 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 216700 kb
Host smart-b8b6b0a2-cc96-44aa-aabc-cf5b5231394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721695002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2721695002
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.776172515
Short name T198
Test name
Test status
Simulation time 91173142 ps
CPU time 1.19 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 219764 kb
Host smart-b6430df3-c131-4db5-b283-331368afe35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776172515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.776172515
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1154858280
Short name T641
Test name
Test status
Simulation time 43593825 ps
CPU time 1.51 seconds
Started Jun 24 06:31:53 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 217444 kb
Host smart-9fdd6522-ee22-4fa8-802e-0732dbea8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154858280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1154858280
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.2979425470
Short name T312
Test name
Test status
Simulation time 33499711 ps
CPU time 1.26 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:48 PM PDT 24
Peak memory 220352 kb
Host smart-cfd8abd4-746e-444b-83d5-7d52143818f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979425470 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.2979425470
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.1881231770
Short name T661
Test name
Test status
Simulation time 43673419 ps
CPU time 1.59 seconds
Started Jun 24 06:31:51 PM PDT 24
Finished Jun 24 06:31:53 PM PDT 24
Peak memory 216688 kb
Host smart-a0aafab4-9307-4ab8-ad40-772a21199527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881231770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1881231770
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.1793882905
Short name T705
Test name
Test status
Simulation time 37528628 ps
CPU time 1.15 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 218764 kb
Host smart-7028be41-f207-4ae4-9d29-d9835421b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793882905 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.1793882905
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.3624220751
Short name T103
Test name
Test status
Simulation time 259736833 ps
CPU time 2.83 seconds
Started Jun 24 06:31:52 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 219256 kb
Host smart-2638fb9c-09de-4378-813a-8ca6f0393503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624220751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3624220751
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.333244369
Short name T649
Test name
Test status
Simulation time 37075381 ps
CPU time 1.2 seconds
Started Jun 24 06:31:50 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 218208 kb
Host smart-6e6a33dc-5531-4145-b648-aac516921dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333244369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.333244369
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.3023674320
Short name T590
Test name
Test status
Simulation time 247288917 ps
CPU time 3.68 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 219352 kb
Host smart-f475788c-c713-4d1f-91d3-f50c44f495fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023674320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3023674320
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.935031390
Short name T913
Test name
Test status
Simulation time 29208678 ps
CPU time 1.27 seconds
Started Jun 24 06:31:53 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 219968 kb
Host smart-448912d5-5cae-4557-927b-2eefaeae058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935031390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.935031390
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.480410039
Short name T655
Test name
Test status
Simulation time 32413154 ps
CPU time 1.29 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:48 PM PDT 24
Peak memory 216676 kb
Host smart-8de98fe9-06e5-4903-b770-747615cde6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480410039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.480410039
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3101664491
Short name T700
Test name
Test status
Simulation time 21753481 ps
CPU time 1.11 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:48 PM PDT 24
Peak memory 218132 kb
Host smart-79c9d4be-3172-4857-a05b-b3b763ba0634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101664491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3101664491
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.2201979854
Short name T621
Test name
Test status
Simulation time 44249120 ps
CPU time 1.1 seconds
Started Jun 24 06:31:47 PM PDT 24
Finished Jun 24 06:31:49 PM PDT 24
Peak memory 216632 kb
Host smart-b8af06b3-0ca6-4d6b-abe0-0dffb309a92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201979854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2201979854
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.3940471503
Short name T258
Test name
Test status
Simulation time 81285131 ps
CPU time 1.19 seconds
Started Jun 24 06:31:47 PM PDT 24
Finished Jun 24 06:31:49 PM PDT 24
Peak memory 217916 kb
Host smart-c0c508c8-8e9e-416c-a8bf-243b426e970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940471503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.3940471503
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.4076118951
Short name T729
Test name
Test status
Simulation time 87630953 ps
CPU time 1.18 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 216620 kb
Host smart-bfd88322-2dc2-485e-9c83-24942533e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076118951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.4076118951
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.2023221667
Short name T294
Test name
Test status
Simulation time 78105342 ps
CPU time 1.2 seconds
Started Jun 24 06:31:45 PM PDT 24
Finished Jun 24 06:31:47 PM PDT 24
Peak memory 218200 kb
Host smart-73b8708e-67b2-4a46-bb13-2268b980bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023221667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.2023221667
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.2276235744
Short name T388
Test name
Test status
Simulation time 47985741 ps
CPU time 1.55 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 217876 kb
Host smart-505e33bd-d6e8-49ee-aa79-24c72213d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276235744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2276235744
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2797159824
Short name T308
Test name
Test status
Simulation time 23135979 ps
CPU time 1.18 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 218744 kb
Host smart-c3b6576e-1ba2-4557-8daf-1a11344e2f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797159824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2797159824
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.4039983153
Short name T870
Test name
Test status
Simulation time 33310007 ps
CPU time 1.38 seconds
Started Jun 24 06:31:49 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 214640 kb
Host smart-732f6128-eb22-4969-922a-87f443c03c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039983153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4039983153
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1924509839
Short name T538
Test name
Test status
Simulation time 85246789 ps
CPU time 1.19 seconds
Started Jun 24 06:29:19 PM PDT 24
Finished Jun 24 06:29:21 PM PDT 24
Peak memory 219228 kb
Host smart-045989ea-ba56-47c4-8938-9e6fc8c3bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924509839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1924509839
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2572598010
Short name T282
Test name
Test status
Simulation time 45960472 ps
CPU time 1.12 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 06:29:19 PM PDT 24
Peak memory 206164 kb
Host smart-b745ef28-5244-497b-9aa9-6903c6292f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572598010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2572598010
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1326722361
Short name T452
Test name
Test status
Simulation time 11664141 ps
CPU time 0.88 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 215472 kb
Host smart-7c5aa202-c171-495c-a0fd-3bba98e71c4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326722361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1326722361
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4051654449
Short name T746
Test name
Test status
Simulation time 45353228 ps
CPU time 1.06 seconds
Started Jun 24 06:29:16 PM PDT 24
Finished Jun 24 06:29:18 PM PDT 24
Peak memory 216400 kb
Host smart-ef44011c-d953-4640-a122-78f7b9b30d56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051654449 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4051654449
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2509697299
Short name T141
Test name
Test status
Simulation time 35002935 ps
CPU time 1.07 seconds
Started Jun 24 06:29:20 PM PDT 24
Finished Jun 24 06:29:22 PM PDT 24
Peak memory 228984 kb
Host smart-f7bab37f-2c83-461e-897f-9d783e8c4730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509697299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2509697299
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.3406510978
Short name T871
Test name
Test status
Simulation time 26542114 ps
CPU time 1.03 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 06:29:19 PM PDT 24
Peak memory 215072 kb
Host smart-c59b6937-75d4-41af-82ce-8504cfc84b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406510978 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3406510978
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1083277723
Short name T415
Test name
Test status
Simulation time 62176857 ps
CPU time 0.94 seconds
Started Jun 24 06:29:08 PM PDT 24
Finished Jun 24 06:29:09 PM PDT 24
Peak memory 214580 kb
Host smart-e3f0f69d-7618-4b94-947f-b5215ac5e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083277723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1083277723
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3468088678
Short name T489
Test name
Test status
Simulation time 121468819 ps
CPU time 1.83 seconds
Started Jun 24 06:29:13 PM PDT 24
Finished Jun 24 06:29:15 PM PDT 24
Peak memory 214688 kb
Host smart-15789afc-f668-45f1-b291-8b8d8f4bc27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468088678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3468088678
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3484571030
Short name T259
Test name
Test status
Simulation time 121046891970 ps
CPU time 1295.64 seconds
Started Jun 24 06:29:11 PM PDT 24
Finished Jun 24 06:50:48 PM PDT 24
Peak memory 223040 kb
Host smart-89b84040-00e6-495f-9aea-1e50744babec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484571030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3484571030
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.384087397
Short name T556
Test name
Test status
Simulation time 32107502 ps
CPU time 1.33 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:48 PM PDT 24
Peak memory 215088 kb
Host smart-1fb7c028-8076-4541-9313-ac19089b6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384087397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.384087397
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.1325256908
Short name T551
Test name
Test status
Simulation time 99852320 ps
CPU time 1.48 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 218488 kb
Host smart-e53decdc-e0de-4819-8354-a975e952ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325256908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1325256908
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.4151761258
Short name T982
Test name
Test status
Simulation time 48616264 ps
CPU time 1.14 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 217756 kb
Host smart-17d81bcd-4cae-452a-8a8c-92649ac7439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151761258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.4151761258
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.119492209
Short name T38
Test name
Test status
Simulation time 61888749 ps
CPU time 1.04 seconds
Started Jun 24 06:31:45 PM PDT 24
Finished Jun 24 06:31:47 PM PDT 24
Peak memory 216452 kb
Host smart-65c0e954-5982-442c-94f3-293dbe29f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119492209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.119492209
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.840095837
Short name T187
Test name
Test status
Simulation time 24967701 ps
CPU time 1.21 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 218024 kb
Host smart-286be816-7bb3-4f4c-a5f6-bfafaccaa7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840095837 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.840095837
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.574120174
Short name T734
Test name
Test status
Simulation time 538276388 ps
CPU time 4.96 seconds
Started Jun 24 06:31:50 PM PDT 24
Finished Jun 24 06:31:56 PM PDT 24
Peak memory 219884 kb
Host smart-e6d1f579-ad29-4632-a6cd-7ccf1cace171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574120174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.574120174
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.4229071775
Short name T257
Test name
Test status
Simulation time 87245319 ps
CPU time 1.18 seconds
Started Jun 24 06:31:46 PM PDT 24
Finished Jun 24 06:31:47 PM PDT 24
Peak memory 218124 kb
Host smart-cb9cc1f9-f8f7-45d5-971a-4e4c0bf15869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229071775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.4229071775
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.2025794784
Short name T375
Test name
Test status
Simulation time 43798739 ps
CPU time 1.64 seconds
Started Jun 24 06:31:50 PM PDT 24
Finished Jun 24 06:31:52 PM PDT 24
Peak memory 218004 kb
Host smart-8e9a12fc-2328-408f-8f6b-32f41eb0f03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025794784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2025794784
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.3258250175
Short name T992
Test name
Test status
Simulation time 52854699 ps
CPU time 1.3 seconds
Started Jun 24 06:31:47 PM PDT 24
Finished Jun 24 06:31:49 PM PDT 24
Peak memory 215084 kb
Host smart-db0987d5-9023-4a3b-bda3-ef3783b955d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258250175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3258250175
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.2342168238
Short name T431
Test name
Test status
Simulation time 28784736 ps
CPU time 1.3 seconds
Started Jun 24 06:31:48 PM PDT 24
Finished Jun 24 06:31:50 PM PDT 24
Peak memory 218012 kb
Host smart-31ddc915-82ab-421a-bf65-642524265fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342168238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2342168238
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.59550427
Short name T517
Test name
Test status
Simulation time 33250958 ps
CPU time 1.29 seconds
Started Jun 24 06:31:58 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 218504 kb
Host smart-6997621a-1213-4cf2-9714-a1fec80d0943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59550427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.59550427
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.970300398
Short name T366
Test name
Test status
Simulation time 139770730 ps
CPU time 1.14 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:58 PM PDT 24
Peak memory 216728 kb
Host smart-8cea6564-210a-4d2a-83ff-41d83236baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970300398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.970300398
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3288174247
Short name T159
Test name
Test status
Simulation time 37317843 ps
CPU time 1.09 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 218244 kb
Host smart-002780c0-2312-426e-b55b-debe47bc7c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288174247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3288174247
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.1358915762
Short name T44
Test name
Test status
Simulation time 142077659 ps
CPU time 1.2 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 216756 kb
Host smart-bcba780e-7c71-4ddb-aa36-2fc67acb1bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358915762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1358915762
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.1112402906
Short name T757
Test name
Test status
Simulation time 51712419 ps
CPU time 1.24 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 218732 kb
Host smart-f992ffc6-a5e1-43fc-aee5-acb306505768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112402906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.1112402906
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.1074729953
Short name T873
Test name
Test status
Simulation time 49550267 ps
CPU time 1.24 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 218080 kb
Host smart-670dc192-98aa-4501-ad9d-d31d541a2728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074729953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1074729953
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1550402386
Short name T956
Test name
Test status
Simulation time 69218111 ps
CPU time 1.35 seconds
Started Jun 24 06:32:00 PM PDT 24
Finished Jun 24 06:32:01 PM PDT 24
Peak memory 219364 kb
Host smart-7911abd1-8834-4dcc-a9a4-4edd4b39054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550402386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1550402386
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2254147107
Short name T516
Test name
Test status
Simulation time 363092941 ps
CPU time 1.2 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 215268 kb
Host smart-1c6bf97e-889f-49bf-b3ae-d8f198dbd043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254147107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2254147107
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2363519401
Short name T842
Test name
Test status
Simulation time 47653549 ps
CPU time 1.67 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 217680 kb
Host smart-8b1c2aff-747d-4ebb-b856-cd8e8ff2c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363519401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2363519401
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1970457082
Short name T236
Test name
Test status
Simulation time 46304056 ps
CPU time 1.06 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 218372 kb
Host smart-5ff22ae6-4fca-4259-a0d9-17e3041ba74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970457082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1970457082
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2248499532
Short name T552
Test name
Test status
Simulation time 27762926 ps
CPU time 1.13 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 06:29:19 PM PDT 24
Peak memory 206040 kb
Host smart-4096685e-42d5-4ce0-8079-95cd07d65640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248499532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2248499532
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2062370308
Short name T384
Test name
Test status
Simulation time 13442840 ps
CPU time 0.93 seconds
Started Jun 24 06:29:16 PM PDT 24
Finished Jun 24 06:29:17 PM PDT 24
Peak memory 215672 kb
Host smart-1f4ad9c6-7cb9-491d-8d2e-8b2bc817718f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062370308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2062370308
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1979686010
Short name T815
Test name
Test status
Simulation time 33979153 ps
CPU time 0.91 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 214616 kb
Host smart-0d078a75-f0df-4047-a5d7-12a841c9b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979686010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1979686010
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.76772588
Short name T345
Test name
Test status
Simulation time 41427341 ps
CPU time 1.71 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 218104 kb
Host smart-08f6329a-bb56-4100-bb66-6380a19c2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76772588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.76772588
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.59832076
Short name T613
Test name
Test status
Simulation time 23047468 ps
CPU time 1.08 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 06:29:19 PM PDT 24
Peak memory 215004 kb
Host smart-42f5616f-fa3b-4a88-9f99-9b4254e12f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59832076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.59832076
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.4186381030
Short name T355
Test name
Test status
Simulation time 46200686 ps
CPU time 0.92 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 214648 kb
Host smart-6cbc243a-9081-4a35-80a1-81ba9872a299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186381030 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.4186381030
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2953308715
Short name T896
Test name
Test status
Simulation time 948616651 ps
CPU time 4.98 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:24 PM PDT 24
Peak memory 214636 kb
Host smart-a67a6b04-dbce-4333-9eeb-5eeaf866c3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953308715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2953308715
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.918200096
Short name T923
Test name
Test status
Simulation time 349062543672 ps
CPU time 1869.96 seconds
Started Jun 24 06:29:17 PM PDT 24
Finished Jun 24 07:00:28 PM PDT 24
Peak memory 225384 kb
Host smart-2088e0e0-09f5-4bf3-bc2d-b9cc39f4c034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918200096 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.918200096
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_alert.4032464302
Short name T679
Test name
Test status
Simulation time 114961102 ps
CPU time 1.08 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 219088 kb
Host smart-e7bf4964-55b6-4773-ac85-f50ffd17ac71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032464302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.4032464302
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.3703775576
Short name T362
Test name
Test status
Simulation time 50248301 ps
CPU time 0.98 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:58 PM PDT 24
Peak memory 216672 kb
Host smart-e6d59ad9-96a0-48ab-ba14-13383d1221c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703775576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3703775576
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.2566264888
Short name T310
Test name
Test status
Simulation time 24510465 ps
CPU time 1.21 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 219904 kb
Host smart-7da7d83d-d135-48d2-bcbf-0ff973cf32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566264888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.2566264888
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.3328990987
Short name T864
Test name
Test status
Simulation time 51326854 ps
CPU time 1.64 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 217892 kb
Host smart-993dbeae-09aa-4c08-b046-d948a0be7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328990987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3328990987
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.3136445811
Short name T158
Test name
Test status
Simulation time 42217189 ps
CPU time 1.05 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 217976 kb
Host smart-35a6cef2-47c0-49e6-bd22-d7f2ffc54ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136445811 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.3136445811
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.2336529826
Short name T750
Test name
Test status
Simulation time 326264250 ps
CPU time 1.18 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 216636 kb
Host smart-d6064949-d5a3-4745-933a-86619ebd5c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336529826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2336529826
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.4206724240
Short name T774
Test name
Test status
Simulation time 22143397 ps
CPU time 1.08 seconds
Started Jun 24 06:31:54 PM PDT 24
Finished Jun 24 06:31:55 PM PDT 24
Peak memory 218052 kb
Host smart-90a96e27-d035-47fe-8e04-398d27d70396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206724240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.4206724240
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/194.edn_alert.2418199413
Short name T145
Test name
Test status
Simulation time 91220377 ps
CPU time 1.08 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 218012 kb
Host smart-7a45da95-7f2f-4a27-971e-c86624ba2657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418199413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.2418199413
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/195.edn_alert.1343872597
Short name T797
Test name
Test status
Simulation time 146744498 ps
CPU time 1.08 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 218040 kb
Host smart-5f436086-bee5-423a-9377-6fe6cf2c4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343872597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1343872597
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.2562131562
Short name T476
Test name
Test status
Simulation time 83170600 ps
CPU time 1.06 seconds
Started Jun 24 06:31:55 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 214584 kb
Host smart-b47afe5a-17e3-4f55-aad8-ceaf4997bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562131562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2562131562
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2438832930
Short name T964
Test name
Test status
Simulation time 94969448 ps
CPU time 1.09 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 216800 kb
Host smart-aeb23a9c-083d-495b-8a5c-d180f2ae54e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438832930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2438832930
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.3173381978
Short name T718
Test name
Test status
Simulation time 44870945 ps
CPU time 1.13 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:58 PM PDT 24
Peak memory 218004 kb
Host smart-3aa255c3-3b25-4d88-8d7c-08adc8474af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173381978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.3173381978
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.1543169019
Short name T72
Test name
Test status
Simulation time 53456547 ps
CPU time 1.1 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 217092 kb
Host smart-ee659727-c46b-4507-9bf3-4d0edea599e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543169019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1543169019
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3394014794
Short name T929
Test name
Test status
Simulation time 21266136 ps
CPU time 1.15 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 219152 kb
Host smart-0a50cb64-068c-4ba2-9693-aa29b6c01a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394014794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3394014794
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.2727547376
Short name T453
Test name
Test status
Simulation time 31174596 ps
CPU time 1.42 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:58 PM PDT 24
Peak memory 217764 kb
Host smart-444459b5-a1ec-41ea-aa6b-6cf86e5d7b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727547376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2727547376
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1264130369
Short name T179
Test name
Test status
Simulation time 39810317 ps
CPU time 1.08 seconds
Started Jun 24 06:32:00 PM PDT 24
Finished Jun 24 06:32:02 PM PDT 24
Peak memory 220184 kb
Host smart-ebd720b7-934f-474c-a262-c85e42bbc65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264130369 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1264130369
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.2274487376
Short name T297
Test name
Test status
Simulation time 48994881 ps
CPU time 1.95 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 219236 kb
Host smart-b9b9261b-ca36-4b7e-a475-1bff281ee42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274487376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2274487376
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3496862672
Short name T819
Test name
Test status
Simulation time 92768574 ps
CPU time 1.3 seconds
Started Jun 24 06:28:30 PM PDT 24
Finished Jun 24 06:28:32 PM PDT 24
Peak memory 217912 kb
Host smart-f7cfa50c-8e26-4a3e-b8a0-0e6807e2de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496862672 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3496862672
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2442404896
Short name T809
Test name
Test status
Simulation time 54508607 ps
CPU time 0.98 seconds
Started Jun 24 06:28:29 PM PDT 24
Finished Jun 24 06:28:31 PM PDT 24
Peak memory 214592 kb
Host smart-9ff33b26-cb0c-46d4-bf14-39e6e96c0c00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442404896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2442404896
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1719681483
Short name T714
Test name
Test status
Simulation time 17554619 ps
CPU time 0.86 seconds
Started Jun 24 06:28:29 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 215688 kb
Host smart-e6f23bf2-1892-4461-92cf-fdc77a5697c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719681483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1719681483
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.606116625
Short name T946
Test name
Test status
Simulation time 38663881 ps
CPU time 0.97 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 217312 kb
Host smart-ce11ad3d-bfc5-43cd-b8e4-16291b8a5f01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606116625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.606116625
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2723636351
Short name T849
Test name
Test status
Simulation time 35577822 ps
CPU time 0.95 seconds
Started Jun 24 06:28:27 PM PDT 24
Finished Jun 24 06:28:29 PM PDT 24
Peak memory 218792 kb
Host smart-41ebdaf4-d690-42a4-a529-b378419edc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723636351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2723636351
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4274851692
Short name T789
Test name
Test status
Simulation time 51301810 ps
CPU time 1.22 seconds
Started Jun 24 06:28:28 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 216516 kb
Host smart-4b981d5a-99fc-4b91-b184-a141be425e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274851692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4274851692
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2931058182
Short name T619
Test name
Test status
Simulation time 38204087 ps
CPU time 0.97 seconds
Started Jun 24 06:28:24 PM PDT 24
Finished Jun 24 06:28:25 PM PDT 24
Peak memory 223196 kb
Host smart-ee6747e5-2635-4296-9e74-b228b13404bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931058182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2931058182
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.4285962896
Short name T740
Test name
Test status
Simulation time 108285501 ps
CPU time 0.91 seconds
Started Jun 24 06:28:24 PM PDT 24
Finished Jun 24 06:28:25 PM PDT 24
Peak memory 206404 kb
Host smart-ed43dad8-71c5-4c13-bfd8-7256f1da9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285962896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.4285962896
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3326027121
Short name T64
Test name
Test status
Simulation time 1388264500 ps
CPU time 5.09 seconds
Started Jun 24 06:28:27 PM PDT 24
Finished Jun 24 06:28:33 PM PDT 24
Peak memory 235048 kb
Host smart-3eb5afe8-8fc6-48cd-bb68-2afc9d6caf12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326027121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3326027121
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3599896953
Short name T783
Test name
Test status
Simulation time 25794896 ps
CPU time 0.95 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:28 PM PDT 24
Peak memory 214644 kb
Host smart-8102992b-bb0e-4c87-83f5-7654f1049f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599896953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3599896953
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.49591481
Short name T743
Test name
Test status
Simulation time 507603766 ps
CPU time 3.54 seconds
Started Jun 24 06:28:27 PM PDT 24
Finished Jun 24 06:28:32 PM PDT 24
Peak memory 216624 kb
Host smart-213651b0-1068-423a-8912-78250214a348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49591481 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.49591481
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.245055683
Short name T665
Test name
Test status
Simulation time 396853664052 ps
CPU time 1424.8 seconds
Started Jun 24 06:28:30 PM PDT 24
Finished Jun 24 06:52:16 PM PDT 24
Peak memory 222048 kb
Host smart-98876074-30a8-440c-a065-137a4dadb82c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245055683 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.245055683
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3082249849
Short name T307
Test name
Test status
Simulation time 39219570 ps
CPU time 1.25 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 218448 kb
Host smart-569d2092-899e-4a7f-8620-8cbcb547c7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082249849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3082249849
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.894256106
Short name T570
Test name
Test status
Simulation time 17528308 ps
CPU time 0.95 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:28 PM PDT 24
Peak memory 206088 kb
Host smart-daeb4cd4-25df-461b-9089-a2526b38ee91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894256106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.894256106
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1127995693
Short name T222
Test name
Test status
Simulation time 39151276 ps
CPU time 0.88 seconds
Started Jun 24 06:29:28 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 215684 kb
Host smart-4d68ee86-3ebb-489c-8e99-15be62e13d2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127995693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1127995693
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2177109681
Short name T70
Test name
Test status
Simulation time 60695704 ps
CPU time 1.61 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:28 PM PDT 24
Peak memory 218484 kb
Host smart-6755ceb0-b3ba-437f-8b84-a7c14cb92c48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177109681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2177109681
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2702660341
Short name T885
Test name
Test status
Simulation time 35050034 ps
CPU time 0.87 seconds
Started Jun 24 06:29:25 PM PDT 24
Finished Jun 24 06:29:26 PM PDT 24
Peak memory 217756 kb
Host smart-c9305ab1-52a1-42fb-9796-123954f59e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702660341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2702660341
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.992283192
Short name T483
Test name
Test status
Simulation time 412986562 ps
CPU time 4.53 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:23 PM PDT 24
Peak memory 219612 kb
Host smart-a63d0dad-c03f-4b46-9dae-05bc7bf979a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992283192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.992283192
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3716381001
Short name T31
Test name
Test status
Simulation time 32334887 ps
CPU time 0.86 seconds
Started Jun 24 06:29:25 PM PDT 24
Finished Jun 24 06:29:27 PM PDT 24
Peak memory 214916 kb
Host smart-b1427034-25ea-4b87-8f6d-655f846a7371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716381001 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3716381001
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2036640501
Short name T480
Test name
Test status
Simulation time 45049530 ps
CPU time 0.9 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:20 PM PDT 24
Peak memory 214608 kb
Host smart-29e9bf92-c30a-4398-8729-6cc88d14f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036640501 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2036640501
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.4293268140
Short name T252
Test name
Test status
Simulation time 323451200 ps
CPU time 6.43 seconds
Started Jun 24 06:29:18 PM PDT 24
Finished Jun 24 06:29:25 PM PDT 24
Peak memory 217800 kb
Host smart-62ae60d6-5897-4145-bac9-960ff102b57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293268140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4293268140
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3719236022
Short name T758
Test name
Test status
Simulation time 59981503031 ps
CPU time 1516.49 seconds
Started Jun 24 06:29:28 PM PDT 24
Finished Jun 24 06:54:47 PM PDT 24
Peak memory 224292 kb
Host smart-4a0ed22e-44d0-4f16-bdef-f1367b612f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719236022 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3719236022
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1251702058
Short name T409
Test name
Test status
Simulation time 72465085 ps
CPU time 1.43 seconds
Started Jun 24 06:31:59 PM PDT 24
Finished Jun 24 06:32:01 PM PDT 24
Peak memory 217996 kb
Host smart-d0ba9253-5d8d-45c1-aff2-e89bba039d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251702058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1251702058
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3580853911
Short name T532
Test name
Test status
Simulation time 48346837 ps
CPU time 1.26 seconds
Started Jun 24 06:31:56 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 216688 kb
Host smart-4423a274-2d7d-4490-bb25-4cd7d3de05db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580853911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3580853911
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2871120137
Short name T337
Test name
Test status
Simulation time 98319961 ps
CPU time 1.48 seconds
Started Jun 24 06:32:00 PM PDT 24
Finished Jun 24 06:32:02 PM PDT 24
Peak memory 218100 kb
Host smart-2b619e25-df4a-4c27-8c9b-f72aa824ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871120137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2871120137
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1293753243
Short name T860
Test name
Test status
Simulation time 127219249 ps
CPU time 1.41 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 219240 kb
Host smart-fbdeca49-bbdc-4542-a3fd-5978b9b7de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293753243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1293753243
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.564006130
Short name T490
Test name
Test status
Simulation time 71950871 ps
CPU time 2.47 seconds
Started Jun 24 06:31:58 PM PDT 24
Finished Jun 24 06:32:01 PM PDT 24
Peak memory 219440 kb
Host smart-aa41d7eb-f4cc-4f3d-a557-747efadb1468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564006130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.564006130
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.370181475
Short name T886
Test name
Test status
Simulation time 65204339 ps
CPU time 1.45 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 217940 kb
Host smart-fbcc9393-495c-484d-888a-0b8528b38c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370181475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.370181475
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2036695625
Short name T966
Test name
Test status
Simulation time 70869424 ps
CPU time 1.08 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 216676 kb
Host smart-1434025b-9044-47d7-84c3-2e1055bdc6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036695625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2036695625
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2882291667
Short name T23
Test name
Test status
Simulation time 139037360 ps
CPU time 3.02 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:13 PM PDT 24
Peak memory 219876 kb
Host smart-a670429b-c86c-4c83-a889-6703e86d72a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882291667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2882291667
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1852842152
Short name T495
Test name
Test status
Simulation time 91276744 ps
CPU time 1.1 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 218116 kb
Host smart-70c25e04-cd64-496a-8f9a-888491de0276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852842152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1852842152
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4115199795
Short name T816
Test name
Test status
Simulation time 63522906 ps
CPU time 1.7 seconds
Started Jun 24 06:32:01 PM PDT 24
Finished Jun 24 06:32:03 PM PDT 24
Peak memory 217984 kb
Host smart-e1b3f4df-96b4-4575-a2ad-a2e9a2b90b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115199795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4115199795
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3424654250
Short name T86
Test name
Test status
Simulation time 42593871 ps
CPU time 1.12 seconds
Started Jun 24 06:29:24 PM PDT 24
Finished Jun 24 06:29:26 PM PDT 24
Peak memory 215084 kb
Host smart-bafc7c38-c6e4-4773-8cb0-b33d3807201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424654250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3424654250
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.723166169
Short name T359
Test name
Test status
Simulation time 21800138 ps
CPU time 1.07 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 214352 kb
Host smart-6ff87160-4d9e-4071-8b86-dd9ea9b0c938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723166169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.723166169
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1919755502
Short name T171
Test name
Test status
Simulation time 30005655 ps
CPU time 0.83 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:37 PM PDT 24
Peak memory 214836 kb
Host smart-eaaad5a9-3adc-4b8c-b058-5378bc6f8ac3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919755502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1919755502
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.420769713
Short name T549
Test name
Test status
Simulation time 79445316 ps
CPU time 1 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:28 PM PDT 24
Peak memory 217540 kb
Host smart-4e89a5b4-1442-4b2e-b050-c93402d68cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420769713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.420769713
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4245497998
Short name T408
Test name
Test status
Simulation time 38447120 ps
CPU time 0.87 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 217924 kb
Host smart-0aaa68b2-7ff3-4293-8a3a-4eda41e83604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245497998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4245497998
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1830103513
Short name T353
Test name
Test status
Simulation time 22162259 ps
CPU time 1.21 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 216492 kb
Host smart-57f7147f-6b6d-4488-b339-74e59546e278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830103513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1830103513
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.548765982
Short name T518
Test name
Test status
Simulation time 24348109 ps
CPU time 1.21 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 223352 kb
Host smart-b9b0b47f-879d-4f6e-a052-248cfc1535a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548765982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.548765982
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.394447435
Short name T352
Test name
Test status
Simulation time 16799252 ps
CPU time 0.96 seconds
Started Jun 24 06:29:33 PM PDT 24
Finished Jun 24 06:29:35 PM PDT 24
Peak memory 214572 kb
Host smart-116d1f29-c5c7-419f-89bc-69687a730a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394447435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.394447435
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.723831325
Short name T795
Test name
Test status
Simulation time 373877071 ps
CPU time 2.91 seconds
Started Jun 24 06:29:28 PM PDT 24
Finished Jun 24 06:29:33 PM PDT 24
Peak memory 214692 kb
Host smart-32e78d53-01bf-483c-8176-1819c922d890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723831325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.723831325
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2375649894
Short name T859
Test name
Test status
Simulation time 37831237515 ps
CPU time 236.22 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:33:24 PM PDT 24
Peak memory 222396 kb
Host smart-e03c92e9-3088-469c-8e01-b2024b748000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375649894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2375649894
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3032398863
Short name T618
Test name
Test status
Simulation time 99426252 ps
CPU time 1.12 seconds
Started Jun 24 06:31:57 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 216668 kb
Host smart-52f78466-49dc-4c24-b074-92683727915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032398863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3032398863
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3679047790
Short name T46
Test name
Test status
Simulation time 66073276 ps
CPU time 1.71 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 218140 kb
Host smart-7d20bdbb-81fa-480b-ac09-7cfb285d76b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679047790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3679047790
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.508317985
Short name T482
Test name
Test status
Simulation time 74327588 ps
CPU time 1.33 seconds
Started Jun 24 06:32:03 PM PDT 24
Finished Jun 24 06:32:04 PM PDT 24
Peak memory 219100 kb
Host smart-4f016dfb-927c-4bd5-9290-c1160133f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508317985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.508317985
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2186446705
Short name T389
Test name
Test status
Simulation time 68824295 ps
CPU time 1.95 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:06 PM PDT 24
Peak memory 217988 kb
Host smart-c875f079-f42f-4202-9915-959126e00f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186446705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2186446705
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.234218853
Short name T392
Test name
Test status
Simulation time 222016666 ps
CPU time 1.27 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 218252 kb
Host smart-cb7d2fbd-ffb2-4695-aa96-c83ccfd745d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234218853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.234218853
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3617122447
Short name T387
Test name
Test status
Simulation time 39236316 ps
CPU time 1.55 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 219600 kb
Host smart-db14eaaa-9530-4c16-bafe-2e1e7a53c9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617122447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3617122447
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1295406469
Short name T303
Test name
Test status
Simulation time 32105481 ps
CPU time 1.5 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 216920 kb
Host smart-1bfa656d-ec90-4122-af8c-24893e00c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295406469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1295406469
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2314882455
Short name T854
Test name
Test status
Simulation time 81775927 ps
CPU time 1.15 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 216628 kb
Host smart-a0923c14-2495-4b0e-9959-d8b0868aad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314882455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2314882455
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2499436178
Short name T690
Test name
Test status
Simulation time 38298001 ps
CPU time 1.26 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 218912 kb
Host smart-6ae7ce61-1ca0-4eff-813e-69c743c4dabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499436178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2499436178
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3975688816
Short name T436
Test name
Test status
Simulation time 77264184 ps
CPU time 1.06 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 217820 kb
Host smart-9baf1af8-cae8-4c3a-b082-5319d0ef9cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975688816 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3975688816
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2889982512
Short name T780
Test name
Test status
Simulation time 42834357 ps
CPU time 0.89 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 206132 kb
Host smart-9e19c7a6-5101-47e3-a6e5-787da831725c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889982512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2889982512
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.66959433
Short name T658
Test name
Test status
Simulation time 169015188 ps
CPU time 1.19 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 216280 kb
Host smart-5f3bb45c-2d6c-4dcc-8dff-3d3e52298236
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66959433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_dis
able_auto_req_mode.66959433
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2555087314
Short name T545
Test name
Test status
Simulation time 148876150 ps
CPU time 1.06 seconds
Started Jun 24 06:29:28 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 218000 kb
Host smart-49c84eb8-1543-4275-9e21-1aca28c62187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555087314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2555087314
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3948581530
Short name T441
Test name
Test status
Simulation time 57659888 ps
CPU time 1.89 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 217980 kb
Host smart-42fdcef4-0b66-43aa-a310-e2a14d37ced2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948581530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3948581530
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1347584635
Short name T487
Test name
Test status
Simulation time 24957964 ps
CPU time 1.12 seconds
Started Jun 24 06:29:28 PM PDT 24
Finished Jun 24 06:29:31 PM PDT 24
Peak memory 223364 kb
Host smart-a1501638-b8b3-43eb-80ae-0dbc49af8dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347584635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1347584635
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.689313506
Short name T391
Test name
Test status
Simulation time 42390843 ps
CPU time 0.95 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 214624 kb
Host smart-4536b663-591f-4631-b07e-1414b0cf163b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689313506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.689313506
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3497460329
Short name T625
Test name
Test status
Simulation time 53721765 ps
CPU time 1.68 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:33 PM PDT 24
Peak memory 214620 kb
Host smart-1abdbe2c-7552-403d-bdd6-a58f2d8a44b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497460329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3497460329
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.583924912
Short name T555
Test name
Test status
Simulation time 103700609226 ps
CPU time 668.87 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:40:38 PM PDT 24
Peak memory 222892 kb
Host smart-8c611876-20f4-4759-832a-0817c71734b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583924912 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.583924912
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/222.edn_genbits.797024060
Short name T419
Test name
Test status
Simulation time 57496680 ps
CPU time 1.4 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:06 PM PDT 24
Peak memory 218036 kb
Host smart-f7bf9d81-b7af-4f0a-b88c-cb0da0a73d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797024060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.797024060
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2864108046
Short name T605
Test name
Test status
Simulation time 49138337 ps
CPU time 1.73 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 217796 kb
Host smart-df68cf5f-b57d-41bf-a75e-04960bea79ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864108046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2864108046
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.666148456
Short name T321
Test name
Test status
Simulation time 47602860 ps
CPU time 1.24 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 217900 kb
Host smart-6d5f0093-782e-4fd4-bb86-3593aed915e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666148456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.666148456
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2115864124
Short name T719
Test name
Test status
Simulation time 40871250 ps
CPU time 1.47 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 216828 kb
Host smart-a539dc81-1096-442f-a958-53d986646e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115864124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2115864124
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.4016740811
Short name T500
Test name
Test status
Simulation time 224188239 ps
CPU time 2.97 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:13 PM PDT 24
Peak memory 219092 kb
Host smart-d1a62610-c70c-44f5-a0de-80de1c914097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016740811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.4016740811
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1368808176
Short name T817
Test name
Test status
Simulation time 34668779 ps
CPU time 1.22 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 218936 kb
Host smart-5d54ab18-5220-49f3-b892-7d253a449fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368808176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1368808176
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2348311289
Short name T36
Test name
Test status
Simulation time 98073958 ps
CPU time 1.06 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 216588 kb
Host smart-d571f489-b4c9-4b13-b05c-9ea5d2f23c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348311289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2348311289
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.998970980
Short name T580
Test name
Test status
Simulation time 87721803 ps
CPU time 1.64 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:06 PM PDT 24
Peak memory 217924 kb
Host smart-1476aaaf-1841-459b-baea-8d53fc2371a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998970980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.998970980
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3455050157
Short name T813
Test name
Test status
Simulation time 49690813 ps
CPU time 1.17 seconds
Started Jun 24 06:29:24 PM PDT 24
Finished Jun 24 06:29:26 PM PDT 24
Peak memory 218088 kb
Host smart-b6000afa-5674-42d3-b5b4-05d06026350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455050157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3455050157
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1866416571
Short name T627
Test name
Test status
Simulation time 86820961 ps
CPU time 0.99 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 206180 kb
Host smart-f0eaabe6-0ac1-4d05-a58a-cfb101c44d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866416571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1866416571
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3474249162
Short name T818
Test name
Test status
Simulation time 12389634 ps
CPU time 0.91 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 214968 kb
Host smart-f3c9ec0e-2ad2-4ae9-b870-b64bb424392f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474249162 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3474249162
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.1463731281
Short name T879
Test name
Test status
Simulation time 31267474 ps
CPU time 1.17 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 214780 kb
Host smart-a6f74d7d-fd9e-41c9-9d67-a9c261563478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463731281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1463731281
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3452086511
Short name T730
Test name
Test status
Simulation time 24214386 ps
CPU time 1.18 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:33 PM PDT 24
Peak memory 216728 kb
Host smart-c130ee7a-a028-4125-add5-0b1971dd55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452086511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3452086511
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4252629208
Short name T788
Test name
Test status
Simulation time 33047372 ps
CPU time 0.86 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 214600 kb
Host smart-82b185ce-2697-43c8-944b-d36bd82bdefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252629208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4252629208
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3588912566
Short name T477
Test name
Test status
Simulation time 74260194 ps
CPU time 0.86 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:32 PM PDT 24
Peak memory 214604 kb
Host smart-207918b6-ca50-4e90-8d94-b5d9be3306f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588912566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3588912566
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3042531030
Short name T741
Test name
Test status
Simulation time 265382781 ps
CPU time 5.31 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:34 PM PDT 24
Peak memory 216620 kb
Host smart-17889c41-8f4d-4800-8e13-c6e95fcc4819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042531030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3042531030
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3498396550
Short name T242
Test name
Test status
Simulation time 174485768646 ps
CPU time 2145.89 seconds
Started Jun 24 06:29:32 PM PDT 24
Finished Jun 24 07:05:19 PM PDT 24
Peak memory 226060 kb
Host smart-c85ab8a5-2dc7-441d-943f-cf0fc9a545fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498396550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3498396550
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2510967974
Short name T602
Test name
Test status
Simulation time 93371889 ps
CPU time 1.19 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 217964 kb
Host smart-bcff3402-4769-452e-b8a6-d79dafe15c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510967974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2510967974
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2201628836
Short name T466
Test name
Test status
Simulation time 39814233 ps
CPU time 1.13 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 216576 kb
Host smart-9c80f2a6-9065-47e8-87b4-40e56773ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201628836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2201628836
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1851346738
Short name T897
Test name
Test status
Simulation time 34575058 ps
CPU time 1.4 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 219212 kb
Host smart-121d0292-a028-4f81-9794-4e164a6dbf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851346738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1851346738
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2077368643
Short name T916
Test name
Test status
Simulation time 119481507 ps
CPU time 1.56 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 218116 kb
Host smart-d58593ee-3b2e-4558-aec0-f88ea85d675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077368643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2077368643
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.878516514
Short name T937
Test name
Test status
Simulation time 84833982 ps
CPU time 1.38 seconds
Started Jun 24 06:32:04 PM PDT 24
Finished Jun 24 06:32:06 PM PDT 24
Peak memory 216692 kb
Host smart-a17ece1d-d0a3-479a-af6f-e96f77c25789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878516514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.878516514
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3650313191
Short name T951
Test name
Test status
Simulation time 69014989 ps
CPU time 1.21 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 216512 kb
Host smart-64c14513-0452-4f63-8c2f-058b2776a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650313191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3650313191
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1725704750
Short name T358
Test name
Test status
Simulation time 36391978 ps
CPU time 1.18 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 216884 kb
Host smart-1951a2bf-a210-4654-b03d-5bfa16db74eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725704750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1725704750
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3375728466
Short name T725
Test name
Test status
Simulation time 335424177 ps
CPU time 4.06 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 217900 kb
Host smart-9fe40422-6d55-43c3-93d4-f280753f154a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375728466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3375728466
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.356078775
Short name T781
Test name
Test status
Simulation time 116404363 ps
CPU time 1.19 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 216780 kb
Host smart-76f22e55-7618-4d0e-98eb-b6844bd8fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356078775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.356078775
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1099269500
Short name T371
Test name
Test status
Simulation time 37460926 ps
CPU time 1.17 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 217924 kb
Host smart-46e4ce79-fa74-4675-8acb-b05217421be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099269500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1099269500
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3600418567
Short name T749
Test name
Test status
Simulation time 64936447 ps
CPU time 1.34 seconds
Started Jun 24 06:29:33 PM PDT 24
Finished Jun 24 06:29:35 PM PDT 24
Peak memory 218140 kb
Host smart-18112b4d-f20f-47f2-8772-3dee54e85cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600418567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3600418567
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3872433251
Short name T833
Test name
Test status
Simulation time 24057935 ps
CPU time 0.87 seconds
Started Jun 24 06:29:42 PM PDT 24
Finished Jun 24 06:29:44 PM PDT 24
Peak memory 214264 kb
Host smart-efe3fcc8-eaac-4f99-a461-6b5cc5d55363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872433251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3872433251
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1388983366
Short name T574
Test name
Test status
Simulation time 11374124 ps
CPU time 0.88 seconds
Started Jun 24 06:29:34 PM PDT 24
Finished Jun 24 06:29:36 PM PDT 24
Peak memory 215656 kb
Host smart-ef108ccd-e3db-45ad-8512-04900a404649
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388983366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1388983366
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1528778236
Short name T135
Test name
Test status
Simulation time 138923919 ps
CPU time 1.28 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:40 PM PDT 24
Peak memory 216272 kb
Host smart-87446be5-afe7-4958-928a-b5e952925d17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528778236 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1528778236
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1232109753
Short name T957
Test name
Test status
Simulation time 38837219 ps
CPU time 1.39 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:30 PM PDT 24
Peak memory 215020 kb
Host smart-85958271-625c-4dc0-be2a-f95d5ab49402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232109753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1232109753
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.651449500
Short name T874
Test name
Test status
Simulation time 81806591 ps
CPU time 1.16 seconds
Started Jun 24 06:29:29 PM PDT 24
Finished Jun 24 06:29:33 PM PDT 24
Peak memory 216748 kb
Host smart-a5bea68e-4598-4ba6-a743-e36cc6ad85f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651449500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.651449500
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2127670541
Short name T124
Test name
Test status
Simulation time 26563316 ps
CPU time 0.89 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:28 PM PDT 24
Peak memory 214976 kb
Host smart-e5652679-c55a-4255-9b29-07eef8ba3649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127670541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2127670541
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.392739154
Short name T699
Test name
Test status
Simulation time 104348715 ps
CPU time 0.94 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:29:28 PM PDT 24
Peak memory 206424 kb
Host smart-09d76125-9963-4654-ac1c-4970d689d3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392739154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.392739154
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3839082278
Short name T594
Test name
Test status
Simulation time 215322194 ps
CPU time 4.74 seconds
Started Jun 24 06:29:27 PM PDT 24
Finished Jun 24 06:29:33 PM PDT 24
Peak memory 216604 kb
Host smart-bdfb0233-0cf6-4de0-82df-0486d554033f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839082278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3839082278
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3714013591
Short name T955
Test name
Test status
Simulation time 338637105832 ps
CPU time 473.54 seconds
Started Jun 24 06:29:26 PM PDT 24
Finished Jun 24 06:37:21 PM PDT 24
Peak memory 218700 kb
Host smart-6b70e8e2-e5bc-4f07-9c35-ac6c8ddfe6f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714013591 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3714013591
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.4039888494
Short name T410
Test name
Test status
Simulation time 66148101 ps
CPU time 1.11 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 218056 kb
Host smart-72fd811a-958a-4484-ba35-fc2c041c5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039888494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.4039888494
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.4234357883
Short name T666
Test name
Test status
Simulation time 38728885 ps
CPU time 1.38 seconds
Started Jun 24 06:32:09 PM PDT 24
Finished Jun 24 06:32:13 PM PDT 24
Peak memory 217836 kb
Host smart-16cfa811-7da2-4c02-bf48-1cc95bbf1680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234357883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.4234357883
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3477992877
Short name T405
Test name
Test status
Simulation time 81505517 ps
CPU time 1.14 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 216536 kb
Host smart-9660eb4b-6516-4b13-a2dd-d6f260ae552f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477992877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3477992877
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2243710738
Short name T456
Test name
Test status
Simulation time 302009405 ps
CPU time 2.18 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 218140 kb
Host smart-78dfb627-f3d9-49df-a75b-5167d17e350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243710738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2243710738
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2538510167
Short name T640
Test name
Test status
Simulation time 359239909 ps
CPU time 1.21 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 216720 kb
Host smart-8f888089-35e2-43b5-818a-7ffe421eaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538510167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2538510167
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2217748969
Short name T418
Test name
Test status
Simulation time 79494741 ps
CPU time 1.5 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 217892 kb
Host smart-5a449bd7-dfed-45e7-99ce-5fe8e12f755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217748969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2217748969
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3827029718
Short name T378
Test name
Test status
Simulation time 32776965 ps
CPU time 1.59 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 219264 kb
Host smart-f7ac241d-c88f-4482-be70-0c780e386f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827029718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3827029718
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1063721553
Short name T45
Test name
Test status
Simulation time 93284343 ps
CPU time 1.21 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 216556 kb
Host smart-ccc90a63-074e-4d95-9bf7-4f12c7dcb241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063721553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1063721553
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4264700674
Short name T407
Test name
Test status
Simulation time 36502365 ps
CPU time 1.35 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 216536 kb
Host smart-f22f109f-515b-4b4f-9970-b549b7c421c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264700674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4264700674
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2425933183
Short name T347
Test name
Test status
Simulation time 9130633224 ps
CPU time 124.26 seconds
Started Jun 24 06:32:09 PM PDT 24
Finished Jun 24 06:34:15 PM PDT 24
Peak memory 219740 kb
Host smart-7bb1e4a2-d03b-4fea-ae8c-4044ddbb2eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425933183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2425933183
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3269051516
Short name T119
Test name
Test status
Simulation time 91818366 ps
CPU time 1.11 seconds
Started Jun 24 06:29:36 PM PDT 24
Finished Jun 24 06:29:39 PM PDT 24
Peak memory 218156 kb
Host smart-7113a0f3-37ac-4332-9f28-bd80efc8e97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269051516 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3269051516
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2666846238
Short name T381
Test name
Test status
Simulation time 57631184 ps
CPU time 0.95 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:39 PM PDT 24
Peak memory 214596 kb
Host smart-15d36399-3d9b-4a0e-8901-0dc3de10a8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666846238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2666846238
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3172787336
Short name T183
Test name
Test status
Simulation time 24140042 ps
CPU time 0.96 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:37 PM PDT 24
Peak memory 215844 kb
Host smart-ca1edfca-5f56-469a-9ac0-a9008849b778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172787336 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3172787336
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.944979704
Short name T771
Test name
Test status
Simulation time 46864605 ps
CPU time 1.07 seconds
Started Jun 24 06:29:42 PM PDT 24
Finished Jun 24 06:29:44 PM PDT 24
Peak memory 217420 kb
Host smart-5e979fce-f038-484a-85cf-f3d31b37f64a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944979704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.944979704
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3104153587
Short name T133
Test name
Test status
Simulation time 35957260 ps
CPU time 1.21 seconds
Started Jun 24 06:29:40 PM PDT 24
Finished Jun 24 06:29:42 PM PDT 24
Peak memory 229036 kb
Host smart-143aa702-6313-487f-810d-7711885056fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104153587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3104153587
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1490299047
Short name T380
Test name
Test status
Simulation time 60924410 ps
CPU time 1.4 seconds
Started Jun 24 06:29:38 PM PDT 24
Finished Jun 24 06:29:41 PM PDT 24
Peak memory 218120 kb
Host smart-bb8f9904-a41c-4524-8abe-211e7910a3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490299047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1490299047
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1848119542
Short name T111
Test name
Test status
Simulation time 23638011 ps
CPU time 1.01 seconds
Started Jun 24 06:29:36 PM PDT 24
Finished Jun 24 06:29:38 PM PDT 24
Peak memory 215116 kb
Host smart-6eab5e74-8c1b-4b5a-a21d-a22d298fd120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848119542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1848119542
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1612393430
Short name T473
Test name
Test status
Simulation time 46878006 ps
CPU time 0.95 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:37 PM PDT 24
Peak memory 214680 kb
Host smart-a12243c8-d7ed-47da-acd0-cc010e7676b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612393430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1612393430
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2671409472
Short name T863
Test name
Test status
Simulation time 308730303 ps
CPU time 3.52 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:42 PM PDT 24
Peak memory 214632 kb
Host smart-9fd8b8bf-f87a-4c30-848f-71b8b87c4007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671409472 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2671409472
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2949268567
Short name T239
Test name
Test status
Simulation time 65844328220 ps
CPU time 394.54 seconds
Started Jun 24 06:29:40 PM PDT 24
Finished Jun 24 06:36:16 PM PDT 24
Peak memory 218128 kb
Host smart-20bd782e-b238-4d46-8398-bfdf8bf8f29c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949268567 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2949268567
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1272081158
Short name T728
Test name
Test status
Simulation time 35241254 ps
CPU time 1.51 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 217652 kb
Host smart-2d67651e-eb50-4998-9c6a-ebdb1cac62ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272081158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1272081158
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3997864610
Short name T696
Test name
Test status
Simulation time 56651728 ps
CPU time 1.4 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:07 PM PDT 24
Peak memory 218152 kb
Host smart-78763c7e-2549-4021-a194-17e742b05065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997864610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3997864610
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1631451565
Short name T614
Test name
Test status
Simulation time 56609734 ps
CPU time 1.25 seconds
Started Jun 24 06:32:09 PM PDT 24
Finished Jun 24 06:32:13 PM PDT 24
Peak memory 214724 kb
Host smart-24caa571-d616-4dca-a889-61b8c52da1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631451565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1631451565
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.391756340
Short name T11
Test name
Test status
Simulation time 38079021 ps
CPU time 1.47 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 219140 kb
Host smart-43ddeddf-1110-4be2-84a6-f2686b8de01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391756340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.391756340
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2728467588
Short name T360
Test name
Test status
Simulation time 61086728 ps
CPU time 1.43 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 217780 kb
Host smart-53e910dd-b4c3-4db1-b71d-0697a660157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728467588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2728467588
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.666046
Short name T248
Test name
Test status
Simulation time 87189524 ps
CPU time 3.08 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 218304 kb
Host smart-df1a56f5-89cb-4cc0-9f79-ac64c66e0f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.666046
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4123759793
Short name T706
Test name
Test status
Simulation time 43617387 ps
CPU time 1.27 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 216468 kb
Host smart-4e449fe2-2cfd-44c7-a04c-5d0a9c3625d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123759793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4123759793
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2673085670
Short name T991
Test name
Test status
Simulation time 76834516 ps
CPU time 1.39 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 217892 kb
Host smart-043b580c-f625-4690-9be3-dfc6c2fbacf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673085670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2673085670
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2470627916
Short name T663
Test name
Test status
Simulation time 332182390 ps
CPU time 2.93 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 219132 kb
Host smart-30b30bea-14d1-4ddb-a237-4a18607ed09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470627916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2470627916
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3744214041
Short name T687
Test name
Test status
Simulation time 57672174 ps
CPU time 1.13 seconds
Started Jun 24 06:29:36 PM PDT 24
Finished Jun 24 06:29:39 PM PDT 24
Peak memory 218188 kb
Host smart-91bacdd2-ec53-4169-8634-9c0bc2b20f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744214041 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3744214041
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2687077458
Short name T866
Test name
Test status
Simulation time 19858942 ps
CPU time 1.08 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:37 PM PDT 24
Peak memory 214332 kb
Host smart-ed111da3-6eb5-45d9-b692-f9a8489a499f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687077458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2687077458
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1165908781
Short name T889
Test name
Test status
Simulation time 40124704 ps
CPU time 0.84 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:40 PM PDT 24
Peak memory 215816 kb
Host smart-a1940049-2bf2-4cae-a000-b1915e83d46d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165908781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1165908781
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1315339377
Short name T659
Test name
Test status
Simulation time 66953806 ps
CPU time 1.01 seconds
Started Jun 24 06:29:39 PM PDT 24
Finished Jun 24 06:29:41 PM PDT 24
Peak memory 217768 kb
Host smart-24f687f9-7081-4763-99e8-3dcb9888e8fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315339377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1315339377
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1785399839
Short name T440
Test name
Test status
Simulation time 18200608 ps
CPU time 1.09 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:38 PM PDT 24
Peak memory 217848 kb
Host smart-f61538bf-9bf4-42fd-95cb-ab3d7c131106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785399839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1785399839
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.3105654532
Short name T33
Test name
Test status
Simulation time 31337190 ps
CPU time 0.92 seconds
Started Jun 24 06:29:34 PM PDT 24
Finished Jun 24 06:29:36 PM PDT 24
Peak memory 215020 kb
Host smart-7b671ae9-97a0-4225-9f46-30b9aafa7da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105654532 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3105654532
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.566189662
Short name T684
Test name
Test status
Simulation time 19727123 ps
CPU time 1.08 seconds
Started Jun 24 06:29:36 PM PDT 24
Finished Jun 24 06:29:39 PM PDT 24
Peak memory 214628 kb
Host smart-a5b9ea3b-0537-4d34-835a-31f9d959f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566189662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.566189662
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.718263114
Short name T782
Test name
Test status
Simulation time 309972505 ps
CPU time 6.36 seconds
Started Jun 24 06:29:35 PM PDT 24
Finished Jun 24 06:29:43 PM PDT 24
Peak memory 216752 kb
Host smart-c2aa078d-bb56-45a3-ad38-43a22eb098fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718263114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.718263114
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2190499833
Short name T324
Test name
Test status
Simulation time 60110410490 ps
CPU time 362.54 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:35:41 PM PDT 24
Peak memory 220428 kb
Host smart-770ed257-e585-4f74-be82-39af7cd9c6b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190499833 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2190499833
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3689437005
Short name T894
Test name
Test status
Simulation time 170438419 ps
CPU time 2.3 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 219588 kb
Host smart-b318b348-16c7-428d-8c6a-130c3c40f303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689437005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3689437005
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1845113227
Short name T520
Test name
Test status
Simulation time 36710588 ps
CPU time 1.41 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 216512 kb
Host smart-5f8351e9-0ef3-49bc-98ea-433e116a2efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845113227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1845113227
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.4135523873
Short name T829
Test name
Test status
Simulation time 78230550 ps
CPU time 1.28 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:12 PM PDT 24
Peak memory 218092 kb
Host smart-35a0edc2-9e3f-4d70-a2c6-f694fca71991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135523873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.4135523873
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1864587733
Short name T515
Test name
Test status
Simulation time 52035679 ps
CPU time 1.51 seconds
Started Jun 24 06:32:05 PM PDT 24
Finished Jun 24 06:32:08 PM PDT 24
Peak memory 218128 kb
Host smart-0ec77a42-d78a-464d-8321-3d57d31e6289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864587733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1864587733
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3247740812
Short name T664
Test name
Test status
Simulation time 111807767 ps
CPU time 1.16 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 219252 kb
Host smart-d48dd582-893c-4734-876b-1e1689cfce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247740812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3247740812
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3993068186
Short name T399
Test name
Test status
Simulation time 53772114 ps
CPU time 1.86 seconds
Started Jun 24 06:32:08 PM PDT 24
Finished Jun 24 06:32:13 PM PDT 24
Peak memory 217780 kb
Host smart-0224125b-4b72-459a-b60e-9ccfb4880150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993068186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3993068186
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1336131156
Short name T539
Test name
Test status
Simulation time 53402644 ps
CPU time 1.47 seconds
Started Jun 24 06:32:06 PM PDT 24
Finished Jun 24 06:32:10 PM PDT 24
Peak memory 217988 kb
Host smart-f2bdb3a1-e44e-4ab4-bbf0-551c5d703403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336131156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1336131156
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2557148043
Short name T801
Test name
Test status
Simulation time 70380176 ps
CPU time 1.35 seconds
Started Jun 24 06:32:07 PM PDT 24
Finished Jun 24 06:32:11 PM PDT 24
Peak memory 214688 kb
Host smart-6d0ee56d-458b-4f79-be32-31c6f696735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557148043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2557148043
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2120738315
Short name T460
Test name
Test status
Simulation time 37307333 ps
CPU time 1.66 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 217668 kb
Host smart-c1f0f228-6e6b-45c4-bf49-e0d9a2dfffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120738315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2120738315
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2660155043
Short name T470
Test name
Test status
Simulation time 108291877 ps
CPU time 1.17 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:20 PM PDT 24
Peak memory 216748 kb
Host smart-1d795f4d-ff39-4568-a9a2-949e83aab107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660155043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2660155043
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1967986113
Short name T662
Test name
Test status
Simulation time 25846212 ps
CPU time 1.25 seconds
Started Jun 24 06:29:34 PM PDT 24
Finished Jun 24 06:29:37 PM PDT 24
Peak memory 218668 kb
Host smart-e583e740-3b05-4f25-87c4-3a38e7ed65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967986113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1967986113
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1564728838
Short name T846
Test name
Test status
Simulation time 12098450 ps
CPU time 0.83 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 205964 kb
Host smart-00914b85-01b7-494f-bb12-12334134777f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564728838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1564728838
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1125226305
Short name T192
Test name
Test status
Simulation time 12403019 ps
CPU time 0.87 seconds
Started Jun 24 06:29:41 PM PDT 24
Finished Jun 24 06:29:43 PM PDT 24
Peak memory 215652 kb
Host smart-d3a3ea41-8bf2-458b-90e3-47a760693d7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125226305 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1125226305
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.378123554
Short name T195
Test name
Test status
Simulation time 18782097 ps
CPU time 1.15 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:40 PM PDT 24
Peak memory 217936 kb
Host smart-8f8f1cda-9878-427e-bd90-9aac0eaa0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378123554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.378123554
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1093250380
Short name T798
Test name
Test status
Simulation time 36894171 ps
CPU time 1.33 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:40 PM PDT 24
Peak memory 218736 kb
Host smart-42cde17f-2e31-4d23-acc9-1b1abb45b096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093250380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1093250380
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2375492436
Short name T701
Test name
Test status
Simulation time 29473446 ps
CPU time 0.98 seconds
Started Jun 24 06:29:37 PM PDT 24
Finished Jun 24 06:29:40 PM PDT 24
Peak memory 215004 kb
Host smart-eabe804e-a245-4490-871c-ad3b92b262f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375492436 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2375492436
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1369982612
Short name T503
Test name
Test status
Simulation time 20778186 ps
CPU time 0.96 seconds
Started Jun 24 06:29:36 PM PDT 24
Finished Jun 24 06:29:38 PM PDT 24
Peak memory 206416 kb
Host smart-68c307ae-a36f-45bc-b7ef-b49468977204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369982612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1369982612
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2714169885
Short name T963
Test name
Test status
Simulation time 114137641 ps
CPU time 2.91 seconds
Started Jun 24 06:29:39 PM PDT 24
Finished Jun 24 06:29:43 PM PDT 24
Peak memory 216704 kb
Host smart-9f416ddb-02e7-4f47-b791-2f1baacc5191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714169885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2714169885
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.2598356122
Short name T527
Test name
Test status
Simulation time 34301364 ps
CPU time 1.39 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 216596 kb
Host smart-dc238cb5-3d73-424d-a3ff-fa404b7697d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598356122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2598356122
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1198822918
Short name T319
Test name
Test status
Simulation time 31847560 ps
CPU time 1.23 seconds
Started Jun 24 06:32:19 PM PDT 24
Finished Jun 24 06:32:23 PM PDT 24
Peak memory 216680 kb
Host smart-5f14ce20-c744-48bd-9071-2f7a08427794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198822918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1198822918
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3550749745
Short name T524
Test name
Test status
Simulation time 100313766 ps
CPU time 1.26 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 216580 kb
Host smart-7f73ef3e-888c-4b5b-a163-f16baa9d2ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550749745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3550749745
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1492600555
Short name T488
Test name
Test status
Simulation time 71639064 ps
CPU time 1.37 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:19 PM PDT 24
Peak memory 218108 kb
Host smart-ef99bb0f-e642-428b-88f3-2c59cf098c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492600555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1492600555
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3524707763
Short name T462
Test name
Test status
Simulation time 68974440 ps
CPU time 1.14 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:18 PM PDT 24
Peak memory 219276 kb
Host smart-b72f9627-232c-4b2c-ae6c-1aedbe9afd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524707763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3524707763
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.4106820597
Short name T908
Test name
Test status
Simulation time 56090593 ps
CPU time 1.67 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 217664 kb
Host smart-1d8a4991-d699-453a-8a6c-a484dfaaac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106820597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.4106820597
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1147577486
Short name T568
Test name
Test status
Simulation time 138159542 ps
CPU time 1.07 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:15 PM PDT 24
Peak memory 216584 kb
Host smart-4891e686-07f6-493a-ac14-e4a5172122aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147577486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1147577486
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3895137553
Short name T977
Test name
Test status
Simulation time 111258082 ps
CPU time 2.26 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:19 PM PDT 24
Peak memory 219204 kb
Host smart-7145a817-4589-456e-9b8f-7d0f053287ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895137553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3895137553
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.395518001
Short name T984
Test name
Test status
Simulation time 74802339 ps
CPU time 1.37 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 217984 kb
Host smart-40f0bd25-3a7c-47e6-950e-0f3f830bae69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395518001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.395518001
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.4259108239
Short name T521
Test name
Test status
Simulation time 323842710 ps
CPU time 2.96 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:24 PM PDT 24
Peak memory 219664 kb
Host smart-38bec796-1d1b-434b-936e-417f8ac71e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259108239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.4259108239
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.555032233
Short name T376
Test name
Test status
Simulation time 23131783 ps
CPU time 1.2 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:45 PM PDT 24
Peak memory 218128 kb
Host smart-33e02945-009c-454a-a1ff-5a49cb1c9460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555032233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.555032233
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3643545754
Short name T841
Test name
Test status
Simulation time 18352201 ps
CPU time 0.93 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:45 PM PDT 24
Peak memory 214568 kb
Host smart-88f5ac5a-e5c3-40d1-8488-17a543f39d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643545754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3643545754
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1886569872
Short name T235
Test name
Test status
Simulation time 124822576 ps
CPU time 0.84 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:52 PM PDT 24
Peak memory 214820 kb
Host smart-27130331-f30f-4a59-9ad8-04b84f0a5f24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886569872 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1886569872
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1446071703
Short name T150
Test name
Test status
Simulation time 28985770 ps
CPU time 1.25 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 217856 kb
Host smart-f90bc686-049c-4f5b-a812-5832e45a3ed1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446071703 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1446071703
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.993582611
Short name T131
Test name
Test status
Simulation time 20991006 ps
CPU time 1.26 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:45 PM PDT 24
Peak memory 229000 kb
Host smart-638565d6-a669-498c-b37e-2e6183d04bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993582611 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.993582611
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.796425402
Short name T450
Test name
Test status
Simulation time 39577552 ps
CPU time 1.38 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 216580 kb
Host smart-e7695179-6454-49d2-bb38-9576117fcef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796425402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.796425402
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1938839717
Short name T55
Test name
Test status
Simulation time 39869367 ps
CPU time 1.03 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 223372 kb
Host smart-fd7aaff1-87bf-4d98-a8f4-b747c1c3baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938839717 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1938839717
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3324818000
Short name T435
Test name
Test status
Simulation time 16302764 ps
CPU time 0.96 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 214628 kb
Host smart-1e2eb48d-f14f-400c-9869-0a6a9debbe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324818000 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3324818000
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2402043846
Short name T414
Test name
Test status
Simulation time 279483501 ps
CPU time 2.29 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 216748 kb
Host smart-9470806c-44f9-4b17-8774-0cced8f7086d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402043846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2402043846
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.4059006397
Short name T76
Test name
Test status
Simulation time 50940182860 ps
CPU time 587.48 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:39:34 PM PDT 24
Peak memory 217564 kb
Host smart-6d202daa-bc9c-4cf2-b97d-63c8503f04a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059006397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.4059006397
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2411312702
Short name T857
Test name
Test status
Simulation time 53982772 ps
CPU time 1.51 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:20 PM PDT 24
Peak memory 217840 kb
Host smart-430d7517-7743-4df2-b9df-ec022b4efb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411312702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2411312702
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2606481752
Short name T454
Test name
Test status
Simulation time 50159101 ps
CPU time 1.33 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 218924 kb
Host smart-e508e245-e799-418b-a0dc-6e16afacbad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606481752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2606481752
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3299910806
Short name T585
Test name
Test status
Simulation time 192462519 ps
CPU time 1.28 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:16 PM PDT 24
Peak memory 214628 kb
Host smart-a8a3cdb4-7067-4be9-ab3d-4e0b9e4a17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299910806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3299910806
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4050972490
Short name T363
Test name
Test status
Simulation time 96384888 ps
CPU time 1.11 seconds
Started Jun 24 06:32:19 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 216508 kb
Host smart-c0ac4240-b1ea-406a-8e67-6f172ecb9874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050972490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4050972490
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2021227364
Short name T806
Test name
Test status
Simulation time 118253392 ps
CPU time 1.39 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 216680 kb
Host smart-603f6ebd-8b2f-4288-b33d-439534f47ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021227364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2021227364
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.4126356842
Short name T915
Test name
Test status
Simulation time 95503364 ps
CPU time 1.41 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:16 PM PDT 24
Peak memory 218456 kb
Host smart-1e6acb1c-b242-4498-9bff-bbf18b3836c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126356842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.4126356842
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2552762769
Short name T934
Test name
Test status
Simulation time 44282081 ps
CPU time 1.18 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:19 PM PDT 24
Peak memory 216784 kb
Host smart-20bfa8b1-9a2a-472c-a659-9a2414ec4ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552762769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2552762769
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4166846853
Short name T930
Test name
Test status
Simulation time 42687640 ps
CPU time 1.42 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:20 PM PDT 24
Peak memory 216476 kb
Host smart-bd955ae1-6c38-425e-932d-581682f35159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166846853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4166846853
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1689133177
Short name T328
Test name
Test status
Simulation time 111565958 ps
CPU time 2 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:23 PM PDT 24
Peak memory 219288 kb
Host smart-a59dc39d-5fd9-4672-bfd4-92d40dadb1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689133177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1689133177
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2844261416
Short name T474
Test name
Test status
Simulation time 51896514 ps
CPU time 2.06 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 217664 kb
Host smart-38be65af-c366-4746-b6ad-22c5530cec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844261416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2844261416
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.202996763
Short name T945
Test name
Test status
Simulation time 38079529 ps
CPU time 1.16 seconds
Started Jun 24 06:29:42 PM PDT 24
Finished Jun 24 06:29:44 PM PDT 24
Peak memory 220356 kb
Host smart-78206810-e16a-44ab-8a34-54f49ebd6131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202996763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.202996763
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3068110224
Short name T628
Test name
Test status
Simulation time 20453470 ps
CPU time 0.91 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:46 PM PDT 24
Peak memory 206092 kb
Host smart-efc2d0ef-b136-4cff-8ddc-bc7a9b47b38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068110224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3068110224
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1338836538
Short name T589
Test name
Test status
Simulation time 13944068 ps
CPU time 0.94 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 214932 kb
Host smart-823bebb9-9ea8-43f4-b99f-fb92b78a2231
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338836538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1338836538
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2146238556
Short name T599
Test name
Test status
Simulation time 78739838 ps
CPU time 1.04 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:46 PM PDT 24
Peak memory 219064 kb
Host smart-7a78beb8-f37c-4745-b5c7-2289d12bb4bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146238556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2146238556
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1870156849
Short name T737
Test name
Test status
Simulation time 19694514 ps
CPU time 1.19 seconds
Started Jun 24 06:29:42 PM PDT 24
Finished Jun 24 06:29:44 PM PDT 24
Peak memory 223384 kb
Host smart-300676a6-d2f1-4480-a681-3cb1ffbed86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870156849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1870156849
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2824677236
Short name T852
Test name
Test status
Simulation time 47177159 ps
CPU time 1.17 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 216620 kb
Host smart-dc250603-2ff0-4ba8-b12d-600cf78698f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824677236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2824677236
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2953508647
Short name T464
Test name
Test status
Simulation time 26143131 ps
CPU time 1.02 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:54 PM PDT 24
Peak memory 214744 kb
Host smart-0d952042-6203-4b72-8872-a65167140a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953508647 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2953508647
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3976028697
Short name T254
Test name
Test status
Simulation time 54010948 ps
CPU time 0.95 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:53 PM PDT 24
Peak memory 214632 kb
Host smart-236d34c7-7e4e-445f-97ba-c701531cb393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976028697 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3976028697
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1304540486
Short name T249
Test name
Test status
Simulation time 644455819 ps
CPU time 3.81 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 216572 kb
Host smart-41ec857f-503f-427d-93a7-3f60fdbd5a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304540486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1304540486
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1672789951
Short name T607
Test name
Test status
Simulation time 102068372714 ps
CPU time 713.78 seconds
Started Jun 24 06:29:47 PM PDT 24
Finished Jun 24 06:41:42 PM PDT 24
Peak memory 222936 kb
Host smart-a3359218-7cad-4611-9e37-d0617f890d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672789951 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1672789951
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.1231024807
Short name T548
Test name
Test status
Simulation time 159479693 ps
CPU time 3.14 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:23 PM PDT 24
Peak memory 214616 kb
Host smart-7c700d44-275d-41b5-830a-0d24af9cb154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231024807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1231024807
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1135697293
Short name T334
Test name
Test status
Simulation time 54419763 ps
CPU time 1.68 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:18 PM PDT 24
Peak memory 219244 kb
Host smart-278b4964-e710-498a-aaa8-68e5ce47ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135697293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1135697293
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2676943943
Short name T533
Test name
Test status
Simulation time 35150656 ps
CPU time 1.36 seconds
Started Jun 24 06:32:15 PM PDT 24
Finished Jun 24 06:32:17 PM PDT 24
Peak memory 216692 kb
Host smart-0d93b7d7-d44c-4055-b9f4-d5a0b312adc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676943943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2676943943
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3419382571
Short name T646
Test name
Test status
Simulation time 74234818 ps
CPU time 1.42 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:18 PM PDT 24
Peak memory 218504 kb
Host smart-f6b0c6df-28b9-4d94-90e9-91ce496bc6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419382571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3419382571
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3216861544
Short name T438
Test name
Test status
Simulation time 31013083 ps
CPU time 1.3 seconds
Started Jun 24 06:32:17 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 216772 kb
Host smart-b489e2cd-2a7b-45ea-9f44-181123a8b0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216861544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3216861544
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.820760341
Short name T96
Test name
Test status
Simulation time 38486659 ps
CPU time 1.59 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:22 PM PDT 24
Peak memory 217960 kb
Host smart-1a589f92-ce5a-44e4-a530-ee49e892abd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820760341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.820760341
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1964308211
Short name T791
Test name
Test status
Simulation time 91862645 ps
CPU time 1.27 seconds
Started Jun 24 06:32:18 PM PDT 24
Finished Jun 24 06:32:21 PM PDT 24
Peak memory 216600 kb
Host smart-0e887a28-4478-4e00-998d-3e6971d5f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964308211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1964308211
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1235778378
Short name T677
Test name
Test status
Simulation time 65523913 ps
CPU time 1.02 seconds
Started Jun 24 06:32:14 PM PDT 24
Finished Jun 24 06:32:16 PM PDT 24
Peak memory 216564 kb
Host smart-e83ffc04-e6e7-466b-9949-72e932d115d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235778378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1235778378
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1360784452
Short name T727
Test name
Test status
Simulation time 27420207 ps
CPU time 1.19 seconds
Started Jun 24 06:32:16 PM PDT 24
Finished Jun 24 06:32:19 PM PDT 24
Peak memory 217740 kb
Host smart-157419ce-b6ca-40c9-a247-d2369965cb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360784452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1360784452
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.808755643
Short name T154
Test name
Test status
Simulation time 29055620 ps
CPU time 1.21 seconds
Started Jun 24 06:28:28 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 219000 kb
Host smart-66d7b381-deb2-4641-9ec8-1bc07a1ac0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808755643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.808755643
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4000618787
Short name T428
Test name
Test status
Simulation time 16087733 ps
CPU time 0.78 seconds
Started Jun 24 06:28:34 PM PDT 24
Finished Jun 24 06:28:35 PM PDT 24
Peak memory 205832 kb
Host smart-9d2c8e53-8f46-4322-a500-ce467e3539bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000618787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4000618787
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1541601352
Short name T190
Test name
Test status
Simulation time 30277587 ps
CPU time 0.83 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 215692 kb
Host smart-648c2d08-bcc4-4ce9-822c-3501393adf11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541601352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1541601352
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1715422138
Short name T429
Test name
Test status
Simulation time 269693278 ps
CPU time 1.04 seconds
Started Jun 24 06:28:28 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 217552 kb
Host smart-72d31ae0-8311-4cc4-a865-7fef8744c1f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715422138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1715422138
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3052059183
Short name T157
Test name
Test status
Simulation time 135272782 ps
CPU time 1.28 seconds
Started Jun 24 06:28:28 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 224804 kb
Host smart-f4889696-bcc3-40f5-9c0a-15c2c3191fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052059183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3052059183
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2461932622
Short name T569
Test name
Test status
Simulation time 32259725 ps
CPU time 1.3 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 217688 kb
Host smart-017a188c-4fae-4610-ba1c-816c14af5d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461932622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2461932622
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2699136644
Short name T909
Test name
Test status
Simulation time 20002004 ps
CPU time 1.08 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 215072 kb
Host smart-a10f112d-b2c0-40a1-b5a0-996a899b8176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699136644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2699136644
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2309669937
Short name T28
Test name
Test status
Simulation time 19127609 ps
CPU time 1.07 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 206436 kb
Host smart-fd733ba0-cf2b-4aa7-b642-34ad0f1d278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309669937 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2309669937
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.714518208
Short name T20
Test name
Test status
Simulation time 252008055 ps
CPU time 4.48 seconds
Started Jun 24 06:28:36 PM PDT 24
Finished Jun 24 06:28:41 PM PDT 24
Peak memory 234956 kb
Host smart-9e10f113-9240-4586-923f-8413f268c1d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714518208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.714518208
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1357627113
Short name T637
Test name
Test status
Simulation time 60656062 ps
CPU time 0.95 seconds
Started Jun 24 06:28:26 PM PDT 24
Finished Jun 24 06:28:28 PM PDT 24
Peak memory 214616 kb
Host smart-b81b6003-2ce2-4fc1-9607-abdfcfefc010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357627113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1357627113
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2262151607
Short name T367
Test name
Test status
Simulation time 149492771 ps
CPU time 3.21 seconds
Started Jun 24 06:28:27 PM PDT 24
Finished Jun 24 06:28:30 PM PDT 24
Peak memory 216548 kb
Host smart-b1a6348f-6ae9-4a0d-b415-2694dbf0983e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262151607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2262151607
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2533936260
Short name T611
Test name
Test status
Simulation time 164940012872 ps
CPU time 899.09 seconds
Started Jun 24 06:28:25 PM PDT 24
Finished Jun 24 06:43:25 PM PDT 24
Peak memory 221356 kb
Host smart-edc48fb0-0f99-413e-88dd-37680e52718a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533936260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2533936260
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.1192671459
Short name T401
Test name
Test status
Simulation time 15325445 ps
CPU time 0.96 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:45 PM PDT 24
Peak memory 214284 kb
Host smart-282579fa-43d7-4a82-995d-ffd28a6ed864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192671459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1192671459
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.2425980036
Short name T626
Test name
Test status
Simulation time 43006107 ps
CPU time 1.25 seconds
Started Jun 24 06:29:47 PM PDT 24
Finished Jun 24 06:29:50 PM PDT 24
Peak memory 225052 kb
Host smart-199fb4aa-3bb4-4993-878c-e5a4f1762e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425980036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2425980036
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2989273923
Short name T385
Test name
Test status
Simulation time 241352913 ps
CPU time 2.86 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:50 PM PDT 24
Peak memory 219336 kb
Host smart-0f960cf1-e56b-408a-befc-176dca083da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989273923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2989273923
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.402717971
Short name T468
Test name
Test status
Simulation time 23214420 ps
CPU time 1.29 seconds
Started Jun 24 06:29:46 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 223380 kb
Host smart-5106e960-2f34-4e87-827d-99c2cc40d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402717971 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.402717971
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.918229487
Short name T731
Test name
Test status
Simulation time 18322563 ps
CPU time 1.05 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 214632 kb
Host smart-d5d1612f-09d4-4769-b491-fef2d6a93cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918229487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.918229487
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.973173851
Short name T878
Test name
Test status
Simulation time 549485272 ps
CPU time 3.25 seconds
Started Jun 24 06:29:50 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 216648 kb
Host smart-ff876255-075d-4c5f-90c2-73f538205edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973173851 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.973173851
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2274435530
Short name T839
Test name
Test status
Simulation time 428765516398 ps
CPU time 2418.89 seconds
Started Jun 24 06:29:49 PM PDT 24
Finished Jun 24 07:10:08 PM PDT 24
Peak memory 227988 kb
Host smart-7115f778-b474-4d64-ad6a-2dbd72ab9efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274435530 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2274435530
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.2438765230
Short name T985
Test name
Test status
Simulation time 20513823 ps
CPU time 0.95 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:58 PM PDT 24
Peak memory 206240 kb
Host smart-14c53cc3-a5a5-4513-94dc-15c9fdc084cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438765230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2438765230
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2690373010
Short name T610
Test name
Test status
Simulation time 186022787 ps
CPU time 0.94 seconds
Started Jun 24 06:29:48 PM PDT 24
Finished Jun 24 06:29:50 PM PDT 24
Peak memory 214812 kb
Host smart-fcd33178-176e-404d-a108-7419b20bfbfb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690373010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2690373010
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2976117955
Short name T151
Test name
Test status
Simulation time 51009235 ps
CPU time 1.1 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:58 PM PDT 24
Peak memory 219296 kb
Host smart-359bb9d2-215f-4b24-b02d-ac977d635e7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976117955 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2976117955
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1723277603
Short name T218
Test name
Test status
Simulation time 40579602 ps
CPU time 1.12 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 219044 kb
Host smart-e7a80243-2558-416c-933b-aa49a01451de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723277603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1723277603
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3179991034
Short name T255
Test name
Test status
Simulation time 880596838 ps
CPU time 6.95 seconds
Started Jun 24 06:29:47 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 216792 kb
Host smart-4dfb378e-2ccd-40e1-98a0-1f5d6a012125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179991034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3179991034
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.705113572
Short name T56
Test name
Test status
Simulation time 31508618 ps
CPU time 1.03 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 223356 kb
Host smart-ccceafc7-a03b-4148-a4f4-068c1037b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705113572 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.705113572
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1345152062
Short name T567
Test name
Test status
Simulation time 28591344 ps
CPU time 0.95 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:58 PM PDT 24
Peak memory 214800 kb
Host smart-e2b1d45e-7699-4df6-b4e4-1cf23eb183f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345152062 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1345152062
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1640360488
Short name T535
Test name
Test status
Simulation time 121546328 ps
CPU time 2.93 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:30:00 PM PDT 24
Peak memory 218124 kb
Host smart-bd2aed83-1bd6-43a6-8cab-c6f66bd05489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640360488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1640360488
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3366749832
Short name T576
Test name
Test status
Simulation time 59234471261 ps
CPU time 780.78 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:42:55 PM PDT 24
Peak memory 219184 kb
Host smart-a754a9e4-734e-43ef-b277-b64dcf200afd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366749832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3366749832
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1416842770
Short name T496
Test name
Test status
Simulation time 382315860 ps
CPU time 1.41 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:58 PM PDT 24
Peak memory 217760 kb
Host smart-18db6e55-c887-4c19-b356-a93456ee349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416842770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1416842770
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2741079893
Short name T917
Test name
Test status
Simulation time 21799382 ps
CPU time 0.86 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 206096 kb
Host smart-26da569f-5203-484a-b380-442948eefdff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741079893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2741079893
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3236909373
Short name T595
Test name
Test status
Simulation time 59468390 ps
CPU time 0.88 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 214836 kb
Host smart-89b4338c-85a6-4e40-8253-3a29ab4257c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236909373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3236909373
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.661233438
Short name T790
Test name
Test status
Simulation time 98165929 ps
CPU time 0.99 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 217704 kb
Host smart-a751c266-0784-494c-ac99-9e5ff2492853
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661233438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.661233438
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1588083760
Short name T155
Test name
Test status
Simulation time 31800005 ps
CPU time 1.08 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 223424 kb
Host smart-9d269adf-9d7a-4b4c-a4b8-b38573e21aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588083760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1588083760
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2984549479
Short name T335
Test name
Test status
Simulation time 141471251 ps
CPU time 1.97 seconds
Started Jun 24 06:29:43 PM PDT 24
Finished Jun 24 06:29:46 PM PDT 24
Peak memory 219456 kb
Host smart-ec3dc9da-da7c-4125-b0af-2f901777b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984549479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2984549479
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1488881909
Short name T960
Test name
Test status
Simulation time 21301708 ps
CPU time 1.12 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 214940 kb
Host smart-18d5d90a-3288-42fb-bf58-d411f011f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488881909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1488881909
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1127312931
Short name T772
Test name
Test status
Simulation time 16915829 ps
CPU time 0.99 seconds
Started Jun 24 06:29:45 PM PDT 24
Finished Jun 24 06:29:48 PM PDT 24
Peak memory 214612 kb
Host smart-e46753ce-d45c-4ba7-a9fd-1689883fd098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127312931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1127312931
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2462808637
Short name T481
Test name
Test status
Simulation time 367588730 ps
CPU time 3.91 seconds
Started Jun 24 06:29:44 PM PDT 24
Finished Jun 24 06:29:50 PM PDT 24
Peak memory 214740 kb
Host smart-ec9c94af-acc4-4aab-8b9c-db928f095636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462808637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2462808637
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1425084534
Short name T116
Test name
Test status
Simulation time 19852121261 ps
CPU time 229.84 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:33:42 PM PDT 24
Peak memory 218176 kb
Host smart-b4860938-c58e-4da0-9604-85bc70aefd95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425084534 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1425084534
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.1694868279
Short name T306
Test name
Test status
Simulation time 25804911 ps
CPU time 1.34 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 218460 kb
Host smart-d59b77a2-e069-419a-a10f-bb0058e8b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694868279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1694868279
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2728984314
Short name T685
Test name
Test status
Simulation time 20609855 ps
CPU time 1.02 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 206136 kb
Host smart-734e4085-9f06-43cb-931b-6ef8e6e84af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728984314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2728984314
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4252921837
Short name T647
Test name
Test status
Simulation time 12925239 ps
CPU time 0.89 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:53 PM PDT 24
Peak memory 215460 kb
Host smart-67d65279-fddf-4e29-981c-766bae3608d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252921837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4252921837
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1989346507
Short name T144
Test name
Test status
Simulation time 63476090 ps
CPU time 1.23 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 216268 kb
Host smart-99c29b49-ffb8-41db-ad7f-183573aa79de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989346507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1989346507
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3665553518
Short name T426
Test name
Test status
Simulation time 20448989 ps
CPU time 1.11 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:53 PM PDT 24
Peak memory 223592 kb
Host smart-05350494-eded-40be-b41c-0389ef91b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665553518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3665553518
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3041115873
Short name T325
Test name
Test status
Simulation time 50367873 ps
CPU time 1.32 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 214672 kb
Host smart-8be6c9ce-be1b-4816-875a-8a22476b3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041115873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3041115873
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.467851968
Short name T85
Test name
Test status
Simulation time 36402737 ps
CPU time 0.89 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 215000 kb
Host smart-2a8d0e07-b518-485d-8a92-e09e6d23f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467851968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.467851968
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1994736671
Short name T349
Test name
Test status
Simulation time 43968046 ps
CPU time 0.93 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:54 PM PDT 24
Peak memory 214624 kb
Host smart-8446271f-227f-44be-bff5-83eb0ba57ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994736671 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1994736671
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1083771007
Short name T660
Test name
Test status
Simulation time 169987606 ps
CPU time 3.64 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:30:01 PM PDT 24
Peak memory 214648 kb
Host smart-449a791b-3c23-41b5-a9d0-153e5aa5fbd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083771007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1083771007
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.128551221
Short name T843
Test name
Test status
Simulation time 45073049267 ps
CPU time 1145.18 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:49:00 PM PDT 24
Peak memory 221220 kb
Host smart-6519d07a-7e0b-49df-9d58-2466eb43bd17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128551221 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.128551221
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2095798665
Short name T650
Test name
Test status
Simulation time 157476055 ps
CPU time 1.38 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 215088 kb
Host smart-d0a8a4db-8d3c-46bc-8b71-cf208c4ae038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095798665 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2095798665
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3772327429
Short name T877
Test name
Test status
Simulation time 99671409 ps
CPU time 1.04 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:53 PM PDT 24
Peak memory 206136 kb
Host smart-8be34e0d-2d97-4457-a39f-0a58a1b5b95d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772327429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3772327429
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1539221724
Short name T176
Test name
Test status
Simulation time 12970373 ps
CPU time 0.92 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 215840 kb
Host smart-513047ed-b065-49ef-b34a-bf9dd2394be1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539221724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1539221724
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2177863301
Short name T582
Test name
Test status
Simulation time 61195604 ps
CPU time 1.25 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 216232 kb
Host smart-e5690c58-3c6a-4658-8829-b6e134c4298c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177863301 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2177863301
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2348706325
Short name T875
Test name
Test status
Simulation time 23780971 ps
CPU time 1.08 seconds
Started Jun 24 06:29:55 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 223408 kb
Host smart-8a849ead-1336-4cde-86c2-2ec3108f2752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348706325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2348706325
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2101510186
Short name T424
Test name
Test status
Simulation time 45824498 ps
CPU time 1.45 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:58 PM PDT 24
Peak memory 217988 kb
Host smart-6eb4aec1-0377-49e1-b850-1a928b684431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101510186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2101510186
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.181637903
Short name T672
Test name
Test status
Simulation time 35312833 ps
CPU time 0.89 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 214616 kb
Host smart-61619971-b4bc-4a1b-88a3-8a949cb82da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181637903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.181637903
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1834009251
Short name T702
Test name
Test status
Simulation time 593994512 ps
CPU time 4.97 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 214640 kb
Host smart-66642b3a-59af-493f-8f6b-8fb22d26ff05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834009251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1834009251
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3005778341
Short name T62
Test name
Test status
Simulation time 264460494363 ps
CPU time 1673.81 seconds
Started Jun 24 06:29:53 PM PDT 24
Finished Jun 24 06:57:49 PM PDT 24
Peak memory 226620 kb
Host smart-0410ad73-bc28-443e-aec8-45eb6f267bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005778341 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3005778341
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2986261688
Short name T283
Test name
Test status
Simulation time 46701154 ps
CPU time 1.24 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 218728 kb
Host smart-3bdae1db-a5dd-4673-b433-b266a2caa337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986261688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2986261688
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.513162422
Short name T596
Test name
Test status
Simulation time 36062741 ps
CPU time 0.94 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 206068 kb
Host smart-28615b6d-8ff8-4f9c-b651-166fec0db00e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513162422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.513162422
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.4037089084
Short name T713
Test name
Test status
Simulation time 50742594 ps
CPU time 1.18 seconds
Started Jun 24 06:30:05 PM PDT 24
Finished Jun 24 06:30:07 PM PDT 24
Peak memory 217452 kb
Host smart-8b7495d5-6d7e-4302-a3ac-2e5eb93ada9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037089084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.4037089084
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2032700056
Short name T557
Test name
Test status
Simulation time 34639047 ps
CPU time 1.04 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 223224 kb
Host smart-2c887c10-e375-48dc-bcca-0f03f7842cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032700056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2032700056
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1480140750
Short name T47
Test name
Test status
Simulation time 98453155 ps
CPU time 1.51 seconds
Started Jun 24 06:29:52 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 218296 kb
Host smart-80f24fa4-717c-4a79-b4ed-04fbef774c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480140750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1480140750
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.784294546
Short name T629
Test name
Test status
Simulation time 24723731 ps
CPU time 0.94 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 214792 kb
Host smart-46d17f2f-b7ba-40ac-941f-91ffa799ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784294546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.784294546
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.444597947
Short name T448
Test name
Test status
Simulation time 38374428 ps
CPU time 0.9 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 214612 kb
Host smart-33044b0e-930d-42d6-855d-cd844dfa7af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444597947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.444597947
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.3927636183
Short name T390
Test name
Test status
Simulation time 443538755 ps
CPU time 2.7 seconds
Started Jun 24 06:29:51 PM PDT 24
Finished Jun 24 06:29:55 PM PDT 24
Peak memory 216620 kb
Host smart-6f167717-4ca6-407a-98b9-d1ec161fa339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927636183 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3927636183
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1553411407
Short name T382
Test name
Test status
Simulation time 55986422301 ps
CPU time 1299.78 seconds
Started Jun 24 06:29:54 PM PDT 24
Finished Jun 24 06:51:36 PM PDT 24
Peak memory 221416 kb
Host smart-205a41c4-0a6f-4dd9-8940-db3aa7af907a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553411407 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1553411407
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3465651308
Short name T120
Test name
Test status
Simulation time 40857002 ps
CPU time 1.14 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 218148 kb
Host smart-b9c13ed6-1607-4ead-86c3-c0090158231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465651308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3465651308
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.456139494
Short name T519
Test name
Test status
Simulation time 37730751 ps
CPU time 0.81 seconds
Started Jun 24 06:29:58 PM PDT 24
Finished Jun 24 06:29:59 PM PDT 24
Peak memory 205968 kb
Host smart-0945cdd4-f3b3-44a7-89d9-a5f1a3cf4135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456139494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.456139494
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2750192699
Short name T221
Test name
Test status
Simulation time 23050178 ps
CPU time 0.85 seconds
Started Jun 24 06:30:00 PM PDT 24
Finished Jun 24 06:30:02 PM PDT 24
Peak memory 215672 kb
Host smart-46a204d9-816e-481b-8a22-941d0c4374c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750192699 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2750192699
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1676263985
Short name T396
Test name
Test status
Simulation time 37570652 ps
CPU time 1.29 seconds
Started Jun 24 06:30:05 PM PDT 24
Finished Jun 24 06:30:07 PM PDT 24
Peak memory 216152 kb
Host smart-5449a9ef-caa6-407a-a445-79bbe6653d5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676263985 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1676263985
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.931379260
Short name T58
Test name
Test status
Simulation time 34424351 ps
CPU time 1.01 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:04 PM PDT 24
Peak memory 223264 kb
Host smart-3364cca7-3a7d-44d7-b772-9fa1bedc9db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931379260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.931379260
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2959729829
Short name T296
Test name
Test status
Simulation time 75767170 ps
CPU time 1.15 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:05 PM PDT 24
Peak memory 216684 kb
Host smart-8528d327-8ecb-4b09-92ff-003d07c42339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959729829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2959729829
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1561340761
Short name T634
Test name
Test status
Simulation time 36659928 ps
CPU time 0.89 seconds
Started Jun 24 06:30:00 PM PDT 24
Finished Jun 24 06:30:02 PM PDT 24
Peak memory 214996 kb
Host smart-fa0a08e7-e5d9-4246-a7ee-9197aea65974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561340761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1561340761
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1049104866
Short name T786
Test name
Test status
Simulation time 30779179 ps
CPU time 0.92 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 214492 kb
Host smart-d77a1c29-5493-4a45-b5ef-64414470cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049104866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1049104866
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1971360780
Short name T840
Test name
Test status
Simulation time 300967847 ps
CPU time 3.32 seconds
Started Jun 24 06:30:03 PM PDT 24
Finished Jun 24 06:30:07 PM PDT 24
Peak memory 216592 kb
Host smart-36d77fa6-f037-473a-be3e-6512710af307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971360780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1971360780
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.3624927157
Short name T193
Test name
Test status
Simulation time 26030862 ps
CPU time 1.22 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:05 PM PDT 24
Peak memory 217988 kb
Host smart-188b70d4-dab1-4922-b0da-805f3349b349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624927157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3624927157
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2024205560
Short name T584
Test name
Test status
Simulation time 47427481 ps
CPU time 0.92 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 206128 kb
Host smart-26ebc299-7f28-4c96-88d7-260f47a8a8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024205560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2024205560
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.691956999
Short name T952
Test name
Test status
Simulation time 17445712 ps
CPU time 0.82 seconds
Started Jun 24 06:29:59 PM PDT 24
Finished Jun 24 06:30:01 PM PDT 24
Peak memory 215584 kb
Host smart-f0359192-e65c-4f9a-bcce-7a8bc4020ec2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691956999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.691956999
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1341785846
Short name T601
Test name
Test status
Simulation time 32729525 ps
CPU time 1.2 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 219200 kb
Host smart-ed75abb3-327d-4deb-855c-14f82265fafa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341785846 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1341785846
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2466144281
Short name T8
Test name
Test status
Simulation time 43678654 ps
CPU time 0.98 seconds
Started Jun 24 06:30:03 PM PDT 24
Finished Jun 24 06:30:05 PM PDT 24
Peak memory 218144 kb
Host smart-00f61de7-6cbb-4512-9429-b32259a32545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466144281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2466144281
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.4168388010
Short name T361
Test name
Test status
Simulation time 44906468 ps
CPU time 1.16 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 216580 kb
Host smart-887dc99d-fb19-4cbd-b39c-ad58a08289fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168388010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.4168388010
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1442251032
Short name T123
Test name
Test status
Simulation time 27714569 ps
CPU time 0.98 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:04 PM PDT 24
Peak memory 215272 kb
Host smart-b2b950bd-da22-4db0-8d41-1b753d4ba3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442251032 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1442251032
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2364451966
Short name T507
Test name
Test status
Simulation time 21596642 ps
CPU time 0.99 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:03 PM PDT 24
Peak memory 214644 kb
Host smart-af15be88-4672-43f2-a050-3cf7cbfaac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364451966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2364451966
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.4162915326
Short name T773
Test name
Test status
Simulation time 345558105 ps
CPU time 4.09 seconds
Started Jun 24 06:30:04 PM PDT 24
Finished Jun 24 06:30:08 PM PDT 24
Peak memory 214628 kb
Host smart-fe57cf8a-6712-47ac-9b34-3859a703619a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162915326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.4162915326
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1254294884
Short name T850
Test name
Test status
Simulation time 535040399079 ps
CPU time 3829.15 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 07:33:52 PM PDT 24
Peak memory 237688 kb
Host smart-eadb8f1d-3a02-4568-99b2-cb159bb23a1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254294884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1254294884
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3543701395
Short name T936
Test name
Test status
Simulation time 45753961 ps
CPU time 1.33 seconds
Started Jun 24 06:30:12 PM PDT 24
Finished Jun 24 06:30:15 PM PDT 24
Peak memory 220324 kb
Host smart-50c64506-ec81-4508-9687-c9f8bf97d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543701395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3543701395
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.695503331
Short name T635
Test name
Test status
Simulation time 39701630 ps
CPU time 0.9 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:13 PM PDT 24
Peak memory 214612 kb
Host smart-cebc223f-1dc4-412a-a581-d43455d98940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695503331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.695503331
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2944482628
Short name T708
Test name
Test status
Simulation time 51350987 ps
CPU time 1.15 seconds
Started Jun 24 06:30:15 PM PDT 24
Finished Jun 24 06:30:18 PM PDT 24
Peak memory 216392 kb
Host smart-1657d659-33af-45e5-b985-15bfe3f370d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944482628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2944482628
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2496118104
Short name T156
Test name
Test status
Simulation time 75855299 ps
CPU time 1.19 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:13 PM PDT 24
Peak memory 224996 kb
Host smart-9b2213f2-badb-4ee8-8e5d-40bdc340ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496118104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2496118104
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2022036177
Short name T354
Test name
Test status
Simulation time 42332128 ps
CPU time 1.3 seconds
Started Jun 24 06:30:01 PM PDT 24
Finished Jun 24 06:30:04 PM PDT 24
Peak memory 216640 kb
Host smart-5f3a1fe0-d5f3-495b-bfc2-b6e3c0569c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022036177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2022036177
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2506577565
Short name T411
Test name
Test status
Simulation time 21939143 ps
CPU time 1.09 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:14 PM PDT 24
Peak memory 214736 kb
Host smart-b0c50675-b41f-468a-a2f7-584aa7b15829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506577565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2506577565
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2762690400
Short name T612
Test name
Test status
Simulation time 21033001 ps
CPU time 0.91 seconds
Started Jun 24 06:29:59 PM PDT 24
Finished Jun 24 06:30:01 PM PDT 24
Peak memory 214604 kb
Host smart-43c95b1b-548e-479d-9e63-0967a762daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762690400 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2762690400
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3895234513
Short name T350
Test name
Test status
Simulation time 1022951358 ps
CPU time 5.64 seconds
Started Jun 24 06:30:02 PM PDT 24
Finished Jun 24 06:30:09 PM PDT 24
Peak memory 216828 kb
Host smart-0bff1753-4863-4030-8c5c-c4b41b93817a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895234513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3895234513
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.737089622
Short name T739
Test name
Test status
Simulation time 87027985 ps
CPU time 1.19 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 219400 kb
Host smart-f751bb56-07c3-4e53-93fe-e97b1f5327b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737089622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.737089622
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.619360974
Short name T486
Test name
Test status
Simulation time 18404282 ps
CPU time 0.88 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 214300 kb
Host smart-4c5cf8fd-7486-4e7a-8cfc-2a7a47cd6989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619360974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.619360974
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2563156378
Short name T217
Test name
Test status
Simulation time 88236125 ps
CPU time 0.86 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 215804 kb
Host smart-0a67a5cf-6a5f-498d-b630-7734808e2449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563156378 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2563156378
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4238102539
Short name T748
Test name
Test status
Simulation time 142333203 ps
CPU time 1.2 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:13 PM PDT 24
Peak memory 216360 kb
Host smart-531b6772-760c-4d3a-b52e-12b196f18582
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238102539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4238102539
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2378316839
Short name T225
Test name
Test status
Simulation time 29627791 ps
CPU time 0.87 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 218064 kb
Host smart-011410e2-1809-4e3f-98a6-e2febfcad9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378316839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2378316839
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3126225387
Short name T247
Test name
Test status
Simulation time 50910064 ps
CPU time 1.57 seconds
Started Jun 24 06:30:12 PM PDT 24
Finished Jun 24 06:30:16 PM PDT 24
Peak memory 214632 kb
Host smart-8d5fe9a1-e35e-4e1a-9f96-586576a116f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126225387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3126225387
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.552743825
Short name T125
Test name
Test status
Simulation time 37803703 ps
CPU time 0.91 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:14 PM PDT 24
Peak memory 215084 kb
Host smart-dbb94bb8-905a-4968-beaf-8150a44a72c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552743825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.552743825
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1487213613
Short name T624
Test name
Test status
Simulation time 26065963 ps
CPU time 0.98 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 214592 kb
Host smart-0daf7bbc-e09f-4739-9a80-ccf930f96d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487213613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1487213613
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.694270236
Short name T639
Test name
Test status
Simulation time 375436851 ps
CPU time 4.24 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:16 PM PDT 24
Peak memory 214636 kb
Host smart-1ab35ab1-6570-4129-945b-fa4cb7444641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694270236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.694270236
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2768681266
Short name T784
Test name
Test status
Simulation time 88156330902 ps
CPU time 2171.26 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 07:06:23 PM PDT 24
Peak memory 230112 kb
Host smart-ff4ed0c1-713f-47af-9ad0-16130093f661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768681266 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2768681266
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2579168234
Short name T794
Test name
Test status
Simulation time 38358604 ps
CPU time 1.19 seconds
Started Jun 24 06:28:33 PM PDT 24
Finished Jun 24 06:28:35 PM PDT 24
Peak memory 220504 kb
Host smart-095275da-d984-4b3c-b02c-0c6e6715a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579168234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2579168234
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3561331633
Short name T703
Test name
Test status
Simulation time 17284728 ps
CPU time 0.97 seconds
Started Jun 24 06:28:41 PM PDT 24
Finished Jun 24 06:28:42 PM PDT 24
Peak memory 214584 kb
Host smart-3dee4684-d513-429e-9d18-d079c8dd1ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561331633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3561331633
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2102416345
Short name T880
Test name
Test status
Simulation time 21181807 ps
CPU time 1.11 seconds
Started Jun 24 06:28:35 PM PDT 24
Finished Jun 24 06:28:37 PM PDT 24
Peak memory 219220 kb
Host smart-43790e65-e725-4efd-b7db-4173ad9f165d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102416345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2102416345
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3570022790
Short name T16
Test name
Test status
Simulation time 19406160 ps
CPU time 1.19 seconds
Started Jun 24 06:28:40 PM PDT 24
Finished Jun 24 06:28:42 PM PDT 24
Peak memory 223400 kb
Host smart-24b634c6-06bb-4cc7-b740-c8928be215bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570022790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3570022790
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2448394926
Short name T459
Test name
Test status
Simulation time 51827916 ps
CPU time 1.28 seconds
Started Jun 24 06:28:32 PM PDT 24
Finished Jun 24 06:28:34 PM PDT 24
Peak memory 219540 kb
Host smart-6753afa0-b388-4de5-9762-d66e68b66d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448394926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2448394926
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4087075057
Short name T113
Test name
Test status
Simulation time 21085065 ps
CPU time 0.99 seconds
Started Jun 24 06:28:32 PM PDT 24
Finished Jun 24 06:28:34 PM PDT 24
Peak memory 215052 kb
Host smart-816f6421-79f2-4e37-8722-0dbee7ae14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087075057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4087075057
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2652513058
Short name T27
Test name
Test status
Simulation time 15671493 ps
CPU time 0.98 seconds
Started Jun 24 06:28:41 PM PDT 24
Finished Jun 24 06:28:43 PM PDT 24
Peak memory 206412 kb
Host smart-cf7c3ad2-8b2a-4bdd-ab93-ea995af4b444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652513058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2652513058
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3669342056
Short name T65
Test name
Test status
Simulation time 1102046005 ps
CPU time 8.68 seconds
Started Jun 24 06:28:40 PM PDT 24
Finished Jun 24 06:28:50 PM PDT 24
Peak memory 235172 kb
Host smart-9bcd026c-9acd-4085-be78-851a5f0a7913
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669342056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3669342056
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3871877569
Short name T402
Test name
Test status
Simulation time 26490687 ps
CPU time 0.97 seconds
Started Jun 24 06:28:34 PM PDT 24
Finished Jun 24 06:28:36 PM PDT 24
Peak memory 214540 kb
Host smart-9ec489f9-0d95-4dbe-8cb4-806968db5570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871877569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3871877569
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.20552125
Short name T680
Test name
Test status
Simulation time 354703525 ps
CPU time 6.56 seconds
Started Jun 24 06:28:35 PM PDT 24
Finished Jun 24 06:28:42 PM PDT 24
Peak memory 214632 kb
Host smart-424799e7-5416-435e-8105-6f90904a8c84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20552125 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.20552125
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3649164108
Short name T973
Test name
Test status
Simulation time 62789498350 ps
CPU time 254.53 seconds
Started Jun 24 06:28:36 PM PDT 24
Finished Jun 24 06:32:51 PM PDT 24
Peak memory 216672 kb
Host smart-241bed44-773e-42f9-8d0d-73a53ce04f3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649164108 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3649164108
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2484964421
Short name T554
Test name
Test status
Simulation time 31931024 ps
CPU time 1.44 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:15 PM PDT 24
Peak memory 215044 kb
Host smart-22b1e825-b64d-49a7-a75c-92937bbd85d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484964421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2484964421
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2271564407
Short name T395
Test name
Test status
Simulation time 15968884 ps
CPU time 0.97 seconds
Started Jun 24 06:30:16 PM PDT 24
Finished Jun 24 06:30:18 PM PDT 24
Peak memory 206620 kb
Host smart-1da1350b-4b12-4244-bbd7-cf225e2d5a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271564407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2271564407
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1254813706
Short name T229
Test name
Test status
Simulation time 32020497 ps
CPU time 0.8 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:11 PM PDT 24
Peak memory 215884 kb
Host smart-b28ce633-ce03-42c3-8dfb-19d47c2a1a3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254813706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1254813706
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1079498124
Short name T710
Test name
Test status
Simulation time 27676371 ps
CPU time 1.11 seconds
Started Jun 24 06:30:15 PM PDT 24
Finished Jun 24 06:30:17 PM PDT 24
Peak memory 217604 kb
Host smart-5892024f-f7a7-4024-aa59-db9ed1c48a8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079498124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1079498124
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2153371316
Short name T220
Test name
Test status
Simulation time 18793815 ps
CPU time 1.13 seconds
Started Jun 24 06:30:10 PM PDT 24
Finished Jun 24 06:30:12 PM PDT 24
Peak memory 218088 kb
Host smart-42ce1101-3acb-44b9-82d9-0625d080e1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153371316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2153371316
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4135658701
Short name T37
Test name
Test status
Simulation time 95370645 ps
CPU time 1.31 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:14 PM PDT 24
Peak memory 216888 kb
Host smart-c50c825d-825d-496d-81aa-e7bdc5333c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135658701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4135658701
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.137971400
Short name T678
Test name
Test status
Simulation time 25418276 ps
CPU time 1.21 seconds
Started Jun 24 06:30:12 PM PDT 24
Finished Jun 24 06:30:15 PM PDT 24
Peak memory 223348 kb
Host smart-3cd716ee-3c83-4160-bd42-bd6374652675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137971400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.137971400
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1324584714
Short name T577
Test name
Test status
Simulation time 34236912 ps
CPU time 0.93 seconds
Started Jun 24 06:30:08 PM PDT 24
Finished Jun 24 06:30:10 PM PDT 24
Peak memory 214648 kb
Host smart-e8042861-8543-4dbd-8d74-9c91449d6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324584714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1324584714
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2471506296
Short name T981
Test name
Test status
Simulation time 128362243132 ps
CPU time 1435.34 seconds
Started Jun 24 06:30:08 PM PDT 24
Finished Jun 24 06:54:04 PM PDT 24
Peak memory 223892 kb
Host smart-131cd6bc-bf1e-4f3d-b0e4-e24d71f498d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471506296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2471506296
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.4127236303
Short name T793
Test name
Test status
Simulation time 43697705 ps
CPU time 1.26 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 218968 kb
Host smart-08df35fe-5b48-4f04-a688-05539efdc2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127236303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.4127236303
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2344881914
Short name T583
Test name
Test status
Simulation time 33700488 ps
CPU time 0.88 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:22 PM PDT 24
Peak memory 214392 kb
Host smart-5e4df47c-5779-4198-b68a-46736e8b727a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344881914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2344881914
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.331931029
Short name T370
Test name
Test status
Simulation time 30231349 ps
CPU time 0.85 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 215324 kb
Host smart-d08f780f-cde7-42b3-b049-1419658b72ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331931029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.331931029
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2052731936
Short name T143
Test name
Test status
Simulation time 95568672 ps
CPU time 1.16 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 216324 kb
Host smart-0a46e414-c500-455c-af91-d91dd4d17489
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052731936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2052731936
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.96826427
Short name T128
Test name
Test status
Simulation time 32139709 ps
CPU time 1.09 seconds
Started Jun 24 06:30:19 PM PDT 24
Finished Jun 24 06:30:21 PM PDT 24
Peak memory 219832 kb
Host smart-1999df71-5fe4-4241-8af6-689d0b509098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96826427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.96826427
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3461748852
Short name T899
Test name
Test status
Simulation time 35426847 ps
CPU time 1.33 seconds
Started Jun 24 06:30:12 PM PDT 24
Finished Jun 24 06:30:15 PM PDT 24
Peak memory 217668 kb
Host smart-5c34cdfd-560e-408d-86f0-115fe77e4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461748852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3461748852
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2509931289
Short name T491
Test name
Test status
Simulation time 24097127 ps
CPU time 0.96 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 214980 kb
Host smart-6376c273-02b0-459a-a585-be5f67c00e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509931289 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2509931289
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2345346788
Short name T770
Test name
Test status
Simulation time 17931926 ps
CPU time 1.03 seconds
Started Jun 24 06:30:11 PM PDT 24
Finished Jun 24 06:30:13 PM PDT 24
Peak memory 214620 kb
Host smart-44db2f4c-e2c7-4fb9-bb0d-a580c5521a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345346788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2345346788
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.123606464
Short name T114
Test name
Test status
Simulation time 619931246 ps
CPU time 2 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:22 PM PDT 24
Peak memory 214632 kb
Host smart-049d58d2-c3d2-4c59-ba98-eb2a9e8a77bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123606464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.123606464
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2846456147
Short name T243
Test name
Test status
Simulation time 12700951285 ps
CPU time 278.99 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:34:59 PM PDT 24
Peak memory 217524 kb
Host smart-f3ed34a4-c06f-4ee2-8ff3-cd6238a7ab5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846456147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2846456147
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1343766245
Short name T633
Test name
Test status
Simulation time 29562131 ps
CPU time 1.35 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 219040 kb
Host smart-2bbbeffa-1741-4f00-9cc9-4e2f43b4475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343766245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1343766245
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.904409995
Short name T423
Test name
Test status
Simulation time 28954760 ps
CPU time 0.91 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:22 PM PDT 24
Peak memory 206044 kb
Host smart-829caa95-d594-4545-a474-77c8d5e8966b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904409995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.904409995
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1069855957
Short name T184
Test name
Test status
Simulation time 13405382 ps
CPU time 0.88 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 215936 kb
Host smart-6fdef02d-0e6d-44ce-96d5-b3900cf13105
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069855957 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1069855957
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_genbits.3152749929
Short name T953
Test name
Test status
Simulation time 36064367 ps
CPU time 1.32 seconds
Started Jun 24 06:30:18 PM PDT 24
Finished Jun 24 06:30:20 PM PDT 24
Peak memory 216704 kb
Host smart-2a21a981-06a3-4798-b0ba-a2860e5c7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152749929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3152749929
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2212046909
Short name T935
Test name
Test status
Simulation time 50965617 ps
CPU time 0.83 seconds
Started Jun 24 06:30:17 PM PDT 24
Finished Jun 24 06:30:18 PM PDT 24
Peak memory 214928 kb
Host smart-3659ed3b-d924-4f91-b71c-55775366898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212046909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2212046909
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2424883776
Short name T512
Test name
Test status
Simulation time 40194668 ps
CPU time 0.9 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 214580 kb
Host smart-55b3e7bf-0d3a-4a04-a1d4-2703fddceb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424883776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2424883776
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.235189932
Short name T620
Test name
Test status
Simulation time 516548792 ps
CPU time 5.13 seconds
Started Jun 24 06:30:19 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 214652 kb
Host smart-dfbb7016-44e4-46f2-80f7-bf634f010503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235189932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.235189932
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3003709806
Short name T471
Test name
Test status
Simulation time 66282624610 ps
CPU time 811.45 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:43:52 PM PDT 24
Peak memory 219496 kb
Host smart-43060361-59a5-4af8-8aaa-41ea06535f0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003709806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3003709806
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3501500852
Short name T295
Test name
Test status
Simulation time 178131218 ps
CPU time 1.18 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 219128 kb
Host smart-252f18bf-daf8-4d88-b108-7de51cd5576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501500852 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3501500852
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2194907058
Short name T498
Test name
Test status
Simulation time 48521982 ps
CPU time 0.97 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 206344 kb
Host smart-b57c03a8-89a9-457d-91b4-456e99b6adeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194907058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2194907058
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3285563883
Short name T213
Test name
Test status
Simulation time 12325500 ps
CPU time 0.92 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 215888 kb
Host smart-300c1c69-b1a7-4111-987a-35e8119e7d9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285563883 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3285563883
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1148767764
Short name T21
Test name
Test status
Simulation time 42684693 ps
CPU time 1.1 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 217548 kb
Host smart-260177bf-be7a-4a88-8cd0-f86e47e4b185
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148767764 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1148767764
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.268018548
Short name T57
Test name
Test status
Simulation time 30610272 ps
CPU time 1.31 seconds
Started Jun 24 06:30:19 PM PDT 24
Finished Jun 24 06:30:21 PM PDT 24
Peak memory 225036 kb
Host smart-5988a7de-01e2-4697-b11d-325ea2f7d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268018548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.268018548
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2034384245
Short name T447
Test name
Test status
Simulation time 42163805 ps
CPU time 1.55 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 217664 kb
Host smart-a9ef7070-2af4-45aa-80ae-da85249bf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034384245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2034384245
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3537573181
Short name T575
Test name
Test status
Simulation time 27960213 ps
CPU time 0.93 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 214984 kb
Host smart-c9b88e37-fdf9-478d-a57b-a32c7f812f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537573181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3537573181
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2064507072
Short name T523
Test name
Test status
Simulation time 129540370 ps
CPU time 0.91 seconds
Started Jun 24 06:30:20 PM PDT 24
Finished Jun 24 06:30:22 PM PDT 24
Peak memory 214628 kb
Host smart-d7c291de-06b1-4c0b-8b55-ab7d681dddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064507072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2064507072
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.818269027
Short name T675
Test name
Test status
Simulation time 435104131 ps
CPU time 5.11 seconds
Started Jun 24 06:30:17 PM PDT 24
Finished Jun 24 06:30:23 PM PDT 24
Peak memory 216584 kb
Host smart-5b796d33-78c3-4ef1-9a3b-363ea0e51441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818269027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.818269027
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2371788730
Short name T241
Test name
Test status
Simulation time 287616676899 ps
CPU time 546.15 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:39:30 PM PDT 24
Peak memory 218672 kb
Host smart-5750a64c-c75b-4c50-bf83-9a940be0137f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371788730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2371788730
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.3697721606
Short name T451
Test name
Test status
Simulation time 108834576 ps
CPU time 0.86 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 205944 kb
Host smart-469d7b7a-01d5-4f67-8dfc-6c3e8107cb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697721606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3697721606
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.810104207
Short name T636
Test name
Test status
Simulation time 17199370 ps
CPU time 0.81 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 214836 kb
Host smart-43ed7357-ebe5-461f-8957-6dbad6848cf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810104207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.810104207
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1464384376
Short name T572
Test name
Test status
Simulation time 320717282 ps
CPU time 1.26 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:26 PM PDT 24
Peak memory 216352 kb
Host smart-b413aa1e-789a-4d86-81ce-4768c977acd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464384376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1464384376
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1314107099
Short name T182
Test name
Test status
Simulation time 19689321 ps
CPU time 1.18 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:26 PM PDT 24
Peak memory 223400 kb
Host smart-d223ce85-6d6b-4add-97e5-e29eedfacaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314107099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1314107099
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3942190321
Short name T48
Test name
Test status
Simulation time 81771876 ps
CPU time 1.57 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 218204 kb
Host smart-b6140276-dfef-4dce-a712-cfc4fe9389f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942190321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3942190321
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.415826091
Short name T810
Test name
Test status
Simulation time 22686024 ps
CPU time 1.08 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:30:26 PM PDT 24
Peak memory 214996 kb
Host smart-75cefd8e-10a6-4b39-822b-f53e8d2d4b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415826091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.415826091
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2172918969
Short name T118
Test name
Test status
Simulation time 63505709 ps
CPU time 0.9 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:25 PM PDT 24
Peak memory 214592 kb
Host smart-810ae85e-75d2-48ea-8d2f-4048bf5c5809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172918969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2172918969
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1394826773
Short name T329
Test name
Test status
Simulation time 289572522 ps
CPU time 6.01 seconds
Started Jun 24 06:30:21 PM PDT 24
Finished Jun 24 06:30:28 PM PDT 24
Peak memory 218680 kb
Host smart-4ee85b01-90e8-4ff1-ba05-2696da66f6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394826773 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1394826773
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1611822167
Short name T941
Test name
Test status
Simulation time 99539651627 ps
CPU time 1162.06 seconds
Started Jun 24 06:30:22 PM PDT 24
Finished Jun 24 06:49:47 PM PDT 24
Peak memory 222228 kb
Host smart-933b3478-95f4-4a22-8d48-ae432421add8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611822167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1611822167
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.921060133
Short name T654
Test name
Test status
Simulation time 42019731 ps
CPU time 1.28 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 215048 kb
Host smart-dc32a417-c084-48da-bde9-73de5856b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921060133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.921060133
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3491468163
Short name T987
Test name
Test status
Simulation time 25893760 ps
CPU time 0.9 seconds
Started Jun 24 06:30:29 PM PDT 24
Finished Jun 24 06:30:31 PM PDT 24
Peak memory 214308 kb
Host smart-df7cb779-f7d6-4797-9605-e9b9fe1aaf43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491468163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3491468163
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4073885075
Short name T821
Test name
Test status
Simulation time 12246183 ps
CPU time 0.88 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 215672 kb
Host smart-8e897852-e26e-4ca9-9522-926dd52514af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073885075 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4073885075
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1840972757
Short name T169
Test name
Test status
Simulation time 32532460 ps
CPU time 1.21 seconds
Started Jun 24 06:30:28 PM PDT 24
Finished Jun 24 06:30:29 PM PDT 24
Peak memory 219296 kb
Host smart-6f3c4f05-e750-44ca-9d01-7c48c6bbbfcc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840972757 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1840972757
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.310399618
Short name T127
Test name
Test status
Simulation time 24741245 ps
CPU time 1.18 seconds
Started Jun 24 06:30:29 PM PDT 24
Finished Jun 24 06:30:31 PM PDT 24
Peak memory 219996 kb
Host smart-0e2bd41c-b195-4ce3-ae45-d9eecd67b2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310399618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.310399618
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2378815018
Short name T638
Test name
Test status
Simulation time 68936957 ps
CPU time 1.57 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 219412 kb
Host smart-e43431f2-8984-4790-ae67-77fd14b64243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378815018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2378815018
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3929324731
Short name T88
Test name
Test status
Simulation time 24818294 ps
CPU time 0.94 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:32 PM PDT 24
Peak memory 214836 kb
Host smart-bcb930a3-acee-4787-991d-dca84c8b6fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929324731 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3929324731
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2824097799
Short name T632
Test name
Test status
Simulation time 21614022 ps
CPU time 0.93 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 214628 kb
Host smart-e3ae39e5-5c65-4cab-8b75-d438941b8133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824097799 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2824097799
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2463722187
Short name T683
Test name
Test status
Simulation time 53733099 ps
CPU time 1.66 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 214632 kb
Host smart-953876aa-e36e-49e9-aa26-64027b472177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463722187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2463722187
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3171381789
Short name T379
Test name
Test status
Simulation time 134615967082 ps
CPU time 1673.02 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:58:25 PM PDT 24
Peak memory 235556 kb
Host smart-3908cda3-24ff-49d2-8004-9c7ac7c963ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171381789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3171381789
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.749653178
Short name T796
Test name
Test status
Simulation time 41820931 ps
CPU time 1.23 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 218456 kb
Host smart-cbfa7e2d-fc3e-46ff-befb-c8b4607fe4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749653178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.749653178
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4166970401
Short name T75
Test name
Test status
Simulation time 18371837 ps
CPU time 0.97 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 206112 kb
Host smart-9397169d-191f-4835-ae37-6a8421b018b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166970401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4166970401
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.486347562
Short name T91
Test name
Test status
Simulation time 11369059 ps
CPU time 0.94 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:32 PM PDT 24
Peak memory 215664 kb
Host smart-94ac4e7c-8034-43ce-affa-7b7917bb8950
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486347562 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.486347562
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.611896139
Short name T893
Test name
Test status
Simulation time 89584391 ps
CPU time 1.07 seconds
Started Jun 24 06:30:29 PM PDT 24
Finished Jun 24 06:30:30 PM PDT 24
Peak memory 217536 kb
Host smart-4633ddb0-99a0-4c81-9af4-511037a1556d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611896139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.611896139
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.761685686
Short name T81
Test name
Test status
Simulation time 44060220 ps
CPU time 1.13 seconds
Started Jun 24 06:30:29 PM PDT 24
Finished Jun 24 06:30:31 PM PDT 24
Peak memory 218972 kb
Host smart-d8ecdd34-2d2d-4414-b1e7-1ba0bf939397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761685686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.761685686
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1384178266
Short name T891
Test name
Test status
Simulation time 212649280 ps
CPU time 2.51 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 218228 kb
Host smart-7d6c1f27-45df-45c4-8549-e1fbee2dddf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384178266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1384178266
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2051573166
Short name T785
Test name
Test status
Simulation time 34433089 ps
CPU time 0.87 seconds
Started Jun 24 06:30:34 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 214896 kb
Host smart-069cbea7-d356-4720-a3cb-c58b8099a681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051573166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2051573166
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3226978433
Short name T543
Test name
Test status
Simulation time 23376503 ps
CPU time 0.99 seconds
Started Jun 24 06:30:33 PM PDT 24
Finished Jun 24 06:30:35 PM PDT 24
Peak memory 214620 kb
Host smart-70fd147f-40f4-4222-8fa7-cae82994c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226978433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3226978433
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.650775395
Short name T211
Test name
Test status
Simulation time 100647543 ps
CPU time 2.38 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 216560 kb
Host smart-9562aee9-9d25-4bb7-b8d0-f395811a3b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650775395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.650775395
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2840604036
Short name T657
Test name
Test status
Simulation time 70410804754 ps
CPU time 418.85 seconds
Started Jun 24 06:30:33 PM PDT 24
Finished Jun 24 06:37:34 PM PDT 24
Peak memory 222916 kb
Host smart-691dc294-360a-4856-a2fa-fdb2eb48e4b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840604036 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2840604036
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.29947100
Short name T146
Test name
Test status
Simulation time 43929932 ps
CPU time 1.16 seconds
Started Jun 24 06:30:33 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 219184 kb
Host smart-9c7124d3-96bc-4aa1-af89-68f64edb7fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29947100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.29947100
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1940948177
Short name T457
Test name
Test status
Simulation time 83460413 ps
CPU time 0.86 seconds
Started Jun 24 06:30:33 PM PDT 24
Finished Jun 24 06:30:35 PM PDT 24
Peak memory 205844 kb
Host smart-e0b9c215-ba44-4b51-b1c1-148ea213dba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940948177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1940948177
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.831931064
Short name T812
Test name
Test status
Simulation time 34597817 ps
CPU time 1.03 seconds
Started Jun 24 06:30:35 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 217468 kb
Host smart-6bdfb600-621f-4129-8681-eaa328696749
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831931064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.831931064
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2774584636
Short name T82
Test name
Test status
Simulation time 27188002 ps
CPU time 0.88 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 217428 kb
Host smart-57702ceb-974f-4506-bff3-7729acf9e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774584636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2774584636
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2107946971
Short name T443
Test name
Test status
Simulation time 100200502 ps
CPU time 1.56 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 216844 kb
Host smart-83acbb2e-cf6d-4cb3-8743-a4afd1c7bbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107946971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2107946971
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2047127095
Short name T383
Test name
Test status
Simulation time 33836883 ps
CPU time 0.93 seconds
Started Jun 24 06:30:26 PM PDT 24
Finished Jun 24 06:30:28 PM PDT 24
Peak memory 214960 kb
Host smart-e208ddf4-97ad-4276-80ce-5e242111891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047127095 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2047127095
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3471434050
Short name T904
Test name
Test status
Simulation time 56155046 ps
CPU time 0.94 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:32 PM PDT 24
Peak memory 214628 kb
Host smart-56a8f323-3be4-40da-ae24-5306482be339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471434050 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3471434050
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4117527156
Short name T251
Test name
Test status
Simulation time 93148700 ps
CPU time 2.28 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 214612 kb
Host smart-5525485f-ee16-4838-85a9-053a6af9d546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117527156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4117527156
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3387621496
Short name T872
Test name
Test status
Simulation time 177431345936 ps
CPU time 1050.26 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:48:01 PM PDT 24
Peak memory 222960 kb
Host smart-c8f3b5c2-3af8-490e-a69d-a0546971596a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387621496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3387621496
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.415698553
Short name T642
Test name
Test status
Simulation time 23709998 ps
CPU time 1.23 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:32 PM PDT 24
Peak memory 219172 kb
Host smart-d3135a6a-020c-41ae-a8c5-ccb47aaf11f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415698553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.415698553
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.538152257
Short name T53
Test name
Test status
Simulation time 20148406 ps
CPU time 0.83 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 205964 kb
Host smart-f994e646-4e98-44f9-b573-c145cde5c7d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538152257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.538152257
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1985629999
Short name T975
Test name
Test status
Simulation time 24289224 ps
CPU time 0.9 seconds
Started Jun 24 06:30:29 PM PDT 24
Finished Jun 24 06:30:31 PM PDT 24
Peak memory 215964 kb
Host smart-d8494186-8f08-4da0-897b-ce2d67af064d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985629999 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1985629999
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.596707818
Short name T959
Test name
Test status
Simulation time 66760574 ps
CPU time 1.02 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:41 PM PDT 24
Peak memory 217532 kb
Host smart-88f89b45-3261-4509-b9ad-ed503ff6788a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596707818 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.596707818
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3971121127
Short name T180
Test name
Test status
Simulation time 23860868 ps
CPU time 1.03 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:30:35 PM PDT 24
Peak memory 217872 kb
Host smart-4308b210-8d21-45fd-8fb6-df9c0d2f4fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971121127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3971121127
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.4282727416
Short name T95
Test name
Test status
Simulation time 278738359 ps
CPU time 1.04 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 216528 kb
Host smart-d1169b1d-b233-4f00-b63f-aba42d5939ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282727416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4282727416
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2880012922
Short name T528
Test name
Test status
Simulation time 25751067 ps
CPU time 1.1 seconds
Started Jun 24 06:30:30 PM PDT 24
Finished Jun 24 06:30:32 PM PDT 24
Peak memory 223384 kb
Host smart-e236a97c-a7a6-40c6-ad0b-276a9d6ebe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880012922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2880012922
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.301726298
Short name T100
Test name
Test status
Simulation time 157256270 ps
CPU time 0.92 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:33 PM PDT 24
Peak memory 214472 kb
Host smart-ab853186-8474-4725-8123-614317749b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301726298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.301726298
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2469511895
Short name T720
Test name
Test status
Simulation time 357474865 ps
CPU time 3.81 seconds
Started Jun 24 06:30:31 PM PDT 24
Finished Jun 24 06:30:36 PM PDT 24
Peak memory 214736 kb
Host smart-033e5f7e-b341-4b1e-af13-0f93ce925e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469511895 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2469511895
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3912267690
Short name T651
Test name
Test status
Simulation time 25049761804 ps
CPU time 591.94 seconds
Started Jun 24 06:30:32 PM PDT 24
Finished Jun 24 06:40:25 PM PDT 24
Peak memory 222944 kb
Host smart-f9615e5d-f227-4741-92fb-ba0dfaea7c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912267690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3912267690
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.934625304
Short name T256
Test name
Test status
Simulation time 33762793 ps
CPU time 1.4 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 215296 kb
Host smart-1480f2d5-b00f-44eb-8692-972207c37c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934625304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.934625304
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2025970823
Short name T876
Test name
Test status
Simulation time 60062548 ps
CPU time 0.83 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 206260 kb
Host smart-4d9f5804-8e74-4102-bc0a-9bcebd03bf3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025970823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2025970823
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1946789376
Short name T356
Test name
Test status
Simulation time 123203755 ps
CPU time 1.22 seconds
Started Jun 24 06:30:42 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 216276 kb
Host smart-ddef47d2-c53d-4655-bf18-7c04669f9c3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946789376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1946789376
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1723709687
Short name T170
Test name
Test status
Simulation time 28588442 ps
CPU time 1.35 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 225140 kb
Host smart-eed530d4-881c-40fb-9f2e-c9165aaa9804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723709687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1723709687
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3679862101
Short name T316
Test name
Test status
Simulation time 48214770 ps
CPU time 1.32 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 217932 kb
Host smart-06e600ae-6e7c-413c-8b34-74bc88fd94e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679862101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3679862101
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3908324511
Short name T560
Test name
Test status
Simulation time 25321075 ps
CPU time 0.97 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 214700 kb
Host smart-3637bfcd-9641-416e-8e10-56ca1de924b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908324511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3908324511
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2502989370
Short name T928
Test name
Test status
Simulation time 44471349 ps
CPU time 0.96 seconds
Started Jun 24 06:30:44 PM PDT 24
Finished Jun 24 06:30:46 PM PDT 24
Peak memory 214652 kb
Host smart-4d76360e-87e8-4f86-9897-49fbc09f7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502989370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2502989370
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1232160684
Short name T600
Test name
Test status
Simulation time 485438789 ps
CPU time 5.24 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:48 PM PDT 24
Peak memory 216760 kb
Host smart-beace0f2-40eb-446a-bb18-feac6549bfaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232160684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1232160684
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3716785701
Short name T240
Test name
Test status
Simulation time 93014747043 ps
CPU time 517.51 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:39:16 PM PDT 24
Peak memory 218620 kb
Host smart-c9bd4d7a-ea0e-48cc-86a6-6c8ce9a5d53a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716785701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3716785701
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4019237924
Short name T689
Test name
Test status
Simulation time 40762185 ps
CPU time 1.13 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 219208 kb
Host smart-cd92faaa-49cf-4024-9876-6fd759207ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019237924 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4019237924
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.17739623
Short name T364
Test name
Test status
Simulation time 46160635 ps
CPU time 1.05 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:45 PM PDT 24
Peak memory 206216 kb
Host smart-3888d462-a9d3-4de3-b723-451f90da1d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.17739623
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2935630664
Short name T804
Test name
Test status
Simulation time 11215980 ps
CPU time 0.88 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 214844 kb
Host smart-66482d67-274d-44aa-a583-78479b943290
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935630664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2935630664
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3148205142
Short name T210
Test name
Test status
Simulation time 90021872 ps
CPU time 1.13 seconds
Started Jun 24 06:28:46 PM PDT 24
Finished Jun 24 06:28:48 PM PDT 24
Peak memory 216688 kb
Host smart-af07094c-773f-4fe7-900f-60c5312ecdee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148205142 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3148205142
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3674458027
Short name T9
Test name
Test status
Simulation time 33082162 ps
CPU time 1.06 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 219012 kb
Host smart-f78156d7-d01b-4ec4-b628-58cff9406766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674458027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3674458027
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2709273581
Short name T336
Test name
Test status
Simulation time 123055504 ps
CPU time 1.31 seconds
Started Jun 24 06:28:32 PM PDT 24
Finished Jun 24 06:28:34 PM PDT 24
Peak memory 217700 kb
Host smart-45c9a36b-ee0e-4b63-8553-327951a1e376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709273581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2709273581
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3466531526
Short name T715
Test name
Test status
Simulation time 21885808 ps
CPU time 1.2 seconds
Started Jun 24 06:28:41 PM PDT 24
Finished Jun 24 06:28:43 PM PDT 24
Peak memory 223352 kb
Host smart-82d6480c-6311-498c-a25a-547e26f158f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466531526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3466531526
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3441227461
Short name T967
Test name
Test status
Simulation time 52916655 ps
CPU time 0.95 seconds
Started Jun 24 06:28:33 PM PDT 24
Finished Jun 24 06:28:34 PM PDT 24
Peak memory 206432 kb
Host smart-6a08943f-3c43-4de8-9c65-d99abeb4d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441227461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3441227461
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3924511198
Short name T986
Test name
Test status
Simulation time 16451195 ps
CPU time 0.96 seconds
Started Jun 24 06:28:34 PM PDT 24
Finished Jun 24 06:28:35 PM PDT 24
Peak memory 214620 kb
Host smart-e483bbe1-5595-464f-82b2-8ae71b038939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924511198 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3924511198
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3273157195
Short name T553
Test name
Test status
Simulation time 174405413 ps
CPU time 1.56 seconds
Started Jun 24 06:28:34 PM PDT 24
Finished Jun 24 06:28:36 PM PDT 24
Peak memory 216492 kb
Host smart-82544e31-2e27-4c2e-8160-1b594794496f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273157195 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3273157195
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1142330180
Short name T763
Test name
Test status
Simulation time 51351454164 ps
CPU time 1266.72 seconds
Started Jun 24 06:28:35 PM PDT 24
Finished Jun 24 06:49:42 PM PDT 24
Peak memory 222956 kb
Host smart-0263f120-3bcb-4f3f-970b-8f0ee448e1a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142330180 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1142330180
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2926797982
Short name T586
Test name
Test status
Simulation time 25906514 ps
CPU time 1.21 seconds
Started Jun 24 06:30:43 PM PDT 24
Finished Jun 24 06:30:46 PM PDT 24
Peak memory 219544 kb
Host smart-129ee57a-5a23-4eed-a7bc-318d21ecd02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926797982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2926797982
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3576216213
Short name T723
Test name
Test status
Simulation time 31114312 ps
CPU time 0.97 seconds
Started Jun 24 06:30:43 PM PDT 24
Finished Jun 24 06:30:46 PM PDT 24
Peak memory 223132 kb
Host smart-db25e80d-b84e-4f00-93b4-80e4b47de67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576216213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3576216213
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4144246471
Short name T938
Test name
Test status
Simulation time 27866593 ps
CPU time 1.21 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 217956 kb
Host smart-6b29ea0c-fe26-42f9-8ec1-4df9296fe88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144246471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4144246471
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.3437236752
Short name T693
Test name
Test status
Simulation time 45135762 ps
CPU time 1.14 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 220104 kb
Host smart-fc8a851b-d835-4db4-90de-1af101c62a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437236752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.3437236752
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.1376852527
Short name T178
Test name
Test status
Simulation time 31527696 ps
CPU time 1.36 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 225124 kb
Host smart-a6afe374-f17f-48e1-8dae-d315a9934d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376852527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1376852527
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1901727786
Short name T616
Test name
Test status
Simulation time 54402935 ps
CPU time 1.25 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 217912 kb
Host smart-8bd80726-b829-4dc7-a0e7-47b649ff78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901727786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1901727786
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.3562093860
Short name T944
Test name
Test status
Simulation time 30046993 ps
CPU time 1.3 seconds
Started Jun 24 06:30:44 PM PDT 24
Finished Jun 24 06:30:46 PM PDT 24
Peak memory 215076 kb
Host smart-1abff244-b662-4e9c-b057-2795e1aa6254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562093860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.3562093860
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.4197080167
Short name T478
Test name
Test status
Simulation time 22926334 ps
CPU time 0.97 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 218708 kb
Host smart-45db646c-5157-40a7-9599-ae3283956981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197080167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4197080167
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1360867801
Short name T990
Test name
Test status
Simulation time 74452298 ps
CPU time 1.45 seconds
Started Jun 24 06:30:44 PM PDT 24
Finished Jun 24 06:30:47 PM PDT 24
Peak memory 218196 kb
Host smart-7c43eb37-0ca7-48be-8794-096b1bda377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360867801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1360867801
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1868268639
Short name T671
Test name
Test status
Simulation time 30118079 ps
CPU time 1.32 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:41 PM PDT 24
Peak memory 219360 kb
Host smart-20933798-eb60-4952-9ca0-272f8b90ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868268639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1868268639
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2535425849
Short name T530
Test name
Test status
Simulation time 38327167 ps
CPU time 0.79 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:41 PM PDT 24
Peak memory 217964 kb
Host smart-55f13815-3249-4d7c-8609-a5d209b08aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535425849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2535425849
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1389946297
Short name T562
Test name
Test status
Simulation time 39712271 ps
CPU time 1.58 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 214632 kb
Host smart-c00f1fa2-e107-4216-8e8e-bcb862dd68aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389946297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1389946297
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.1837346974
Short name T458
Test name
Test status
Simulation time 42541518 ps
CPU time 1.09 seconds
Started Jun 24 06:30:36 PM PDT 24
Finished Jun 24 06:30:38 PM PDT 24
Peak memory 218460 kb
Host smart-d55a863b-d58a-4603-8c85-ee44aeb53bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837346974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.1837346974
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2031160474
Short name T822
Test name
Test status
Simulation time 29298812 ps
CPU time 1.26 seconds
Started Jun 24 06:30:43 PM PDT 24
Finished Jun 24 06:30:45 PM PDT 24
Peak memory 229144 kb
Host smart-b0b966a4-6329-4fb0-8e32-c58976cf8e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031160474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2031160474
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2545370005
Short name T340
Test name
Test status
Simulation time 122909670 ps
CPU time 2.56 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:45 PM PDT 24
Peak memory 219260 kb
Host smart-ab4a6344-0ada-408f-9e4e-4ddfa75c3d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545370005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2545370005
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.2383072990
Short name T803
Test name
Test status
Simulation time 39700265 ps
CPU time 1.09 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:50 PM PDT 24
Peak memory 219248 kb
Host smart-6ee91550-7254-4363-bcd9-2b698d4e11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383072990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.2383072990
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2670871398
Short name T80
Test name
Test status
Simulation time 26646391 ps
CPU time 0.97 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 218204 kb
Host smart-a14d2c6d-365a-46dd-a112-3f22482acddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670871398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2670871398
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3661371189
Short name T339
Test name
Test status
Simulation time 88533756 ps
CPU time 1.35 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:41 PM PDT 24
Peak memory 217960 kb
Host smart-64e647b9-83aa-485a-a8b3-72e61ad96bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661371189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3661371189
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.2183151777
Short name T835
Test name
Test status
Simulation time 26185803 ps
CPU time 1.15 seconds
Started Jun 24 06:30:42 PM PDT 24
Finished Jun 24 06:30:45 PM PDT 24
Peak memory 220044 kb
Host smart-6afbac52-c739-4d16-a044-d8745703d0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183151777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.2183151777
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2539939092
Short name T147
Test name
Test status
Simulation time 64790815 ps
CPU time 1.2 seconds
Started Jun 24 06:30:42 PM PDT 24
Finished Jun 24 06:30:45 PM PDT 24
Peak memory 220016 kb
Host smart-de343967-5702-4e82-bd9e-71890d296cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539939092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2539939092
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2964667812
Short name T861
Test name
Test status
Simulation time 108588095 ps
CPU time 1.16 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 216720 kb
Host smart-c3026aea-8015-4bc3-8693-f1ff7bb8b6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964667812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2964667812
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.1798862477
Short name T153
Test name
Test status
Simulation time 46783921 ps
CPU time 1.18 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 217896 kb
Host smart-913680e1-21cc-47a1-bd3b-4ed56a8057bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798862477 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.1798862477
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.539656992
Short name T160
Test name
Test status
Simulation time 24855840 ps
CPU time 0.96 seconds
Started Jun 24 06:30:43 PM PDT 24
Finished Jun 24 06:30:46 PM PDT 24
Peak memory 218772 kb
Host smart-029f429c-c83e-4946-8a4d-48234309644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539656992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.539656992
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.736417952
Short name T41
Test name
Test status
Simulation time 82485854 ps
CPU time 1.18 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 216776 kb
Host smart-2b095ecd-886b-4177-8af4-0c5458a8c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736417952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.736417952
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.4209035670
Short name T309
Test name
Test status
Simulation time 33326617 ps
CPU time 1.28 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 215068 kb
Host smart-e78e437f-1c75-4003-9e6c-a991b76b6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209035670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.4209035670
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3501655491
Short name T753
Test name
Test status
Simulation time 30693449 ps
CPU time 1.17 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 219132 kb
Host smart-1d21cdba-faa0-4953-a354-595b7c8acc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501655491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3501655491
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3641938574
Short name T674
Test name
Test status
Simulation time 117492245 ps
CPU time 1.37 seconds
Started Jun 24 06:30:44 PM PDT 24
Finished Jun 24 06:30:47 PM PDT 24
Peak memory 217880 kb
Host smart-0719e0ab-281f-4f90-877c-4441a5e2f059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641938574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3641938574
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2163837898
Short name T855
Test name
Test status
Simulation time 382224872 ps
CPU time 1.32 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:42 PM PDT 24
Peak memory 219888 kb
Host smart-6f55d969-7036-4b4a-949a-bf92f91ba844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163837898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2163837898
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2366885106
Short name T775
Test name
Test status
Simulation time 47752556 ps
CPU time 1.1 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 219116 kb
Host smart-c41b8569-1d5a-4e6b-b6fb-6027172ffbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366885106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2366885106
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.633922263
Short name T475
Test name
Test status
Simulation time 77086150 ps
CPU time 1.18 seconds
Started Jun 24 06:30:38 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 219136 kb
Host smart-ac38536d-1d3f-4380-8023-b2c184386f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633922263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.633922263
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3157401444
Short name T422
Test name
Test status
Simulation time 87681400 ps
CPU time 1.24 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 215028 kb
Host smart-e42a26ea-fd94-4bdc-994a-3ec34273aa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157401444 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3157401444
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2730486911
Short name T505
Test name
Test status
Simulation time 20492908 ps
CPU time 1.02 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 206224 kb
Host smart-7ae5b0bc-45ad-4466-b700-409b4689c87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730486911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2730486911
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.291754201
Short name T479
Test name
Test status
Simulation time 10577306 ps
CPU time 0.89 seconds
Started Jun 24 06:28:45 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 215320 kb
Host smart-e717fc3f-1b62-43cc-8861-d09f5c5a1bae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291754201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.291754201
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2237003373
Short name T215
Test name
Test status
Simulation time 88291252 ps
CPU time 1.16 seconds
Started Jun 24 06:28:45 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 216432 kb
Host smart-1ba99140-ad24-4318-be94-a427001a9656
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237003373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2237003373
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3981602164
Short name T209
Test name
Test status
Simulation time 29278727 ps
CPU time 0.88 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 217660 kb
Host smart-0bda3fe4-2f9b-4e6c-8bd1-4b1f6bd71627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981602164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3981602164
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1696150292
Short name T469
Test name
Test status
Simulation time 51519652 ps
CPU time 1.24 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 217908 kb
Host smart-30a9f417-1856-4b56-9e5e-bf80a5022580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696150292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1696150292
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2273223429
Short name T603
Test name
Test status
Simulation time 61884960 ps
CPU time 0.92 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 214828 kb
Host smart-28707366-01ab-4cf3-9442-4f11ebc24a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273223429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2273223429
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1095054708
Short name T695
Test name
Test status
Simulation time 14282778 ps
CPU time 0.95 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 206420 kb
Host smart-b3f90309-f7a5-4283-84e6-8e89639aa4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095054708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1095054708
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2339856655
Short name T767
Test name
Test status
Simulation time 31195836 ps
CPU time 1.04 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 214648 kb
Host smart-f5ebb93d-d7ac-4e28-bc76-0f7e5547d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339856655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2339856655
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2439241987
Short name T437
Test name
Test status
Simulation time 121189003 ps
CPU time 1.39 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 214640 kb
Host smart-d3bdac7e-d59a-43f0-93ce-b260c1cee1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439241987 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2439241987
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.3733279698
Short name T832
Test name
Test status
Simulation time 56169862 ps
CPU time 1.27 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 219428 kb
Host smart-882c42e1-6b3e-4190-a1bc-d76831b24c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733279698 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.3733279698
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.977826307
Short name T901
Test name
Test status
Simulation time 42589230 ps
CPU time 1 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 223248 kb
Host smart-4c945dd3-70f5-40e9-b733-43ca7264dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977826307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.977826307
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.908978141
Short name T707
Test name
Test status
Simulation time 40650359 ps
CPU time 1.41 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 214640 kb
Host smart-3f14a8fe-83d6-4226-a8e4-95966ebdc3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908978141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.908978141
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.4140306013
Short name T152
Test name
Test status
Simulation time 47351176 ps
CPU time 1.1 seconds
Started Jun 24 06:30:39 PM PDT 24
Finished Jun 24 06:30:41 PM PDT 24
Peak memory 218208 kb
Host smart-da1052e3-4392-491c-b197-192176b5a5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140306013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.4140306013
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.1095093483
Short name T181
Test name
Test status
Simulation time 54537979 ps
CPU time 0.82 seconds
Started Jun 24 06:30:42 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 217740 kb
Host smart-f6db4eb6-3a6d-42ef-a785-c979a7301474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095093483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1095093483
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.716460855
Short name T368
Test name
Test status
Simulation time 29940546 ps
CPU time 1.54 seconds
Started Jun 24 06:30:41 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 218020 kb
Host smart-bc097396-b10c-47ff-ba97-895d03bb9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716460855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.716460855
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4110020483
Short name T63
Test name
Test status
Simulation time 41022073 ps
CPU time 1.1 seconds
Started Jun 24 06:30:40 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 220076 kb
Host smart-d0f6ce84-dcf9-42ac-a91a-a9aa5e98c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110020483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4110020483
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.857400101
Short name T943
Test name
Test status
Simulation time 21558957 ps
CPU time 1.2 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 223596 kb
Host smart-ca710aac-a434-4ad5-b53f-1087c500fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857400101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.857400101
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1806606296
Short name T559
Test name
Test status
Simulation time 35160266 ps
CPU time 1.38 seconds
Started Jun 24 06:30:42 PM PDT 24
Finished Jun 24 06:30:45 PM PDT 24
Peak memory 218720 kb
Host smart-23e56e85-0a59-4ac6-8e08-2144104aed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806606296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1806606296
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.1201678583
Short name T926
Test name
Test status
Simulation time 42463329 ps
CPU time 1.13 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:52 PM PDT 24
Peak memory 218588 kb
Host smart-5e485cbf-4480-4445-9c7f-4379f92294c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201678583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.1201678583
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.3198422707
Short name T219
Test name
Test status
Simulation time 20636985 ps
CPU time 1.2 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:52 PM PDT 24
Peak memory 228992 kb
Host smart-1118b42f-52fd-4f61-9dcc-4243548758c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198422707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3198422707
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1868235257
Short name T511
Test name
Test status
Simulation time 371075108 ps
CPU time 2.28 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:55 PM PDT 24
Peak memory 217940 kb
Host smart-3f15b2e6-5c59-4101-adf0-799deb9153dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868235257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1868235257
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.41869935
Short name T106
Test name
Test status
Simulation time 28914187 ps
CPU time 1.23 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 220064 kb
Host smart-e0af5a66-34ce-4209-863e-32a5cccda166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41869935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.41869935
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.974978696
Short name T231
Test name
Test status
Simulation time 21387221 ps
CPU time 1.19 seconds
Started Jun 24 06:30:52 PM PDT 24
Finished Jun 24 06:30:56 PM PDT 24
Peak memory 228948 kb
Host smart-72183578-0f12-414c-91fe-e13bce0566bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974978696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.974978696
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1439513920
Short name T497
Test name
Test status
Simulation time 170596505 ps
CPU time 1.17 seconds
Started Jun 24 06:30:53 PM PDT 24
Finished Jun 24 06:30:56 PM PDT 24
Peak memory 218192 kb
Host smart-0add6db6-b5bb-4dd2-8b64-d24b7461d2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439513920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1439513920
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2273839659
Short name T800
Test name
Test status
Simulation time 41004719 ps
CPU time 1.1 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 219148 kb
Host smart-0bf4e9d8-4866-4899-b4e6-c3c6d8006e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273839659 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2273839659
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.261289475
Short name T189
Test name
Test status
Simulation time 23494537 ps
CPU time 1.25 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 223380 kb
Host smart-b9854b8e-fa52-46d1-935d-22516472e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261289475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.261289475
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.920061957
Short name T344
Test name
Test status
Simulation time 113458320 ps
CPU time 1.71 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:52 PM PDT 24
Peak memory 218488 kb
Host smart-fbdbfddf-e976-4a32-adf7-128128bb28fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920061957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.920061957
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.1290548597
Short name T756
Test name
Test status
Simulation time 28109055 ps
CPU time 1.23 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 218076 kb
Host smart-abc2605b-3045-4b47-bff0-8c44cb773b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290548597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.1290548597
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2599834877
Short name T449
Test name
Test status
Simulation time 18699498 ps
CPU time 1.04 seconds
Started Jun 24 06:30:53 PM PDT 24
Finished Jun 24 06:30:56 PM PDT 24
Peak memory 217752 kb
Host smart-fbf41aa6-4538-4f1d-ad9f-208e2cebeb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599834877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2599834877
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.953971861
Short name T357
Test name
Test status
Simulation time 54823390 ps
CPU time 1.07 seconds
Started Jun 24 06:30:52 PM PDT 24
Finished Jun 24 06:30:55 PM PDT 24
Peak memory 216964 kb
Host smart-cae33832-743b-4717-b3ab-f7e6f5bb66f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953971861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.953971861
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.3921359353
Short name T824
Test name
Test status
Simulation time 22516114 ps
CPU time 1.14 seconds
Started Jun 24 06:30:52 PM PDT 24
Finished Jun 24 06:30:55 PM PDT 24
Peak memory 218128 kb
Host smart-7519e5c1-913d-49c6-92c4-06d638253ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921359353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.3921359353
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.299502799
Short name T161
Test name
Test status
Simulation time 25288933 ps
CPU time 1.12 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 229000 kb
Host smart-c82055d9-e1c4-4138-842b-625c13fde3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299502799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.299502799
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3191681495
Short name T87
Test name
Test status
Simulation time 41500426 ps
CPU time 1.52 seconds
Started Jun 24 06:30:55 PM PDT 24
Finished Jun 24 06:30:58 PM PDT 24
Peak memory 216636 kb
Host smart-663d7bad-f7fb-4794-b779-16309dc08db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191681495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3191681495
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.584589553
Short name T301
Test name
Test status
Simulation time 98464827 ps
CPU time 1.31 seconds
Started Jun 24 06:30:51 PM PDT 24
Finished Jun 24 06:30:54 PM PDT 24
Peak memory 219228 kb
Host smart-74f312e4-739c-4acd-9f6a-9d99f027ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584589553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.584589553
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.1172167825
Short name T200
Test name
Test status
Simulation time 23028645 ps
CPU time 1.04 seconds
Started Jun 24 06:30:48 PM PDT 24
Finished Jun 24 06:30:50 PM PDT 24
Peak memory 223380 kb
Host smart-2e2b1194-0867-4814-96fd-ea42c4fd8aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172167825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1172167825
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2021507297
Short name T724
Test name
Test status
Simulation time 61487298 ps
CPU time 1.41 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:52 PM PDT 24
Peak memory 216676 kb
Host smart-f035eae0-66c8-48a2-9c83-68362a22420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021507297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2021507297
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.1596110134
Short name T68
Test name
Test status
Simulation time 44318433 ps
CPU time 1.1 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:52 PM PDT 24
Peak memory 219496 kb
Host smart-c8556de1-88cc-47e2-9211-85da76b09bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596110134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.1596110134
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3325145058
Short name T73
Test name
Test status
Simulation time 30229014 ps
CPU time 0.85 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:51 PM PDT 24
Peak memory 218960 kb
Host smart-cb91eb8c-ca47-4af5-8bb0-f62794c47731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325145058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3325145058
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1888067264
Short name T732
Test name
Test status
Simulation time 67025969 ps
CPU time 1.7 seconds
Started Jun 24 06:30:54 PM PDT 24
Finished Jun 24 06:30:57 PM PDT 24
Peak memory 218224 kb
Host smart-c123073d-b91a-4491-b752-9a75c38c67f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888067264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1888067264
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3128684313
Short name T974
Test name
Test status
Simulation time 27475713 ps
CPU time 1.2 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 215068 kb
Host smart-4db8180e-8d3b-4178-9102-a5725a48d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128684313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3128684313
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2173128780
Short name T406
Test name
Test status
Simulation time 49348270 ps
CPU time 0.93 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 206088 kb
Host smart-86793378-eaca-4571-9d83-896e96f3a3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173128780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2173128780
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1089844082
Short name T230
Test name
Test status
Simulation time 13110107 ps
CPU time 0.94 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 215840 kb
Host smart-5c60e251-adec-4fa4-ada1-316a9991df12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089844082 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1089844082
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2759647395
Short name T563
Test name
Test status
Simulation time 20830139 ps
CPU time 0.98 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 217332 kb
Host smart-22f065ee-a20f-4b32-87c6-db941368b79c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759647395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2759647395
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.2608019893
Short name T484
Test name
Test status
Simulation time 27582090 ps
CPU time 1.25 seconds
Started Jun 24 06:28:46 PM PDT 24
Finished Jun 24 06:28:48 PM PDT 24
Peak memory 216952 kb
Host smart-ebbd8586-be72-45c3-b814-418bbae968ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608019893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2608019893
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3201988690
Short name T826
Test name
Test status
Simulation time 27857074 ps
CPU time 0.96 seconds
Started Jun 24 06:28:42 PM PDT 24
Finished Jun 24 06:28:44 PM PDT 24
Peak memory 214792 kb
Host smart-0f6b1a65-cf39-4e6d-af8b-3c8dcd5784bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201988690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3201988690
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3288102080
Short name T593
Test name
Test status
Simulation time 18595353 ps
CPU time 1.06 seconds
Started Jun 24 06:28:46 PM PDT 24
Finished Jun 24 06:28:48 PM PDT 24
Peak memory 206424 kb
Host smart-6ee20e60-c055-406b-a050-4c9abdf48b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288102080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3288102080
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3726807166
Short name T848
Test name
Test status
Simulation time 18349686 ps
CPU time 1.08 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 214624 kb
Host smart-a6864fe3-4c78-4892-bef3-9ecfb2efeaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726807166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3726807166
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.978372585
Short name T892
Test name
Test status
Simulation time 296139582 ps
CPU time 5.55 seconds
Started Jun 24 06:28:45 PM PDT 24
Finished Jun 24 06:28:51 PM PDT 24
Peak memory 214612 kb
Host smart-7df38861-db42-41d6-b205-b8de868dacb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978372585 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.978372585
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2183206427
Short name T34
Test name
Test status
Simulation time 32948488362 ps
CPU time 831.95 seconds
Started Jun 24 06:28:46 PM PDT 24
Finished Jun 24 06:42:39 PM PDT 24
Peak memory 218408 kb
Host smart-58a1a504-c985-4429-ac18-a3d91ab81bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183206427 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2183206427
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_alert.2546361189
Short name T284
Test name
Test status
Simulation time 53135153 ps
CPU time 1.33 seconds
Started Jun 24 06:30:57 PM PDT 24
Finished Jun 24 06:30:59 PM PDT 24
Peak memory 218596 kb
Host smart-a3a010fc-3229-4781-9ba6-2c8e0767ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546361189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2546361189
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.2114047949
Short name T509
Test name
Test status
Simulation time 42604635 ps
CPU time 1.11 seconds
Started Jun 24 06:30:53 PM PDT 24
Finished Jun 24 06:30:56 PM PDT 24
Peak memory 217064 kb
Host smart-31cbd56a-0f1a-44c3-acc2-cc9f4aee24fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114047949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2114047949
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1090792602
Short name T430
Test name
Test status
Simulation time 31827568 ps
CPU time 1.25 seconds
Started Jun 24 06:30:54 PM PDT 24
Finished Jun 24 06:30:57 PM PDT 24
Peak memory 217868 kb
Host smart-09b6e1fa-0749-44d4-9641-47a973d99ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090792602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1090792602
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.851131629
Short name T676
Test name
Test status
Simulation time 105547063 ps
CPU time 1.19 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 218544 kb
Host smart-869ac724-a6f0-42f6-ae9c-f3d2c1e725b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851131629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.851131629
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.3053360166
Short name T174
Test name
Test status
Simulation time 32556732 ps
CPU time 0.87 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 217676 kb
Host smart-8f4b79a7-086a-4dbf-a191-e5e5b44cd8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053360166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3053360166
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1202048507
Short name T922
Test name
Test status
Simulation time 49666014 ps
CPU time 1.48 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 218024 kb
Host smart-ed8a950a-8ea6-448f-9455-16f38692d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202048507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1202048507
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.3198985728
Short name T962
Test name
Test status
Simulation time 88205532 ps
CPU time 1.32 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 215284 kb
Host smart-14bccf3b-edfb-4006-95aa-b5acfdbb4b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198985728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.3198985728
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3391775479
Short name T445
Test name
Test status
Simulation time 29791551 ps
CPU time 0.96 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 223224 kb
Host smart-e534942f-be93-422c-acd4-205bbae095a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391775479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3391775479
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/73.edn_alert.2381911995
Short name T608
Test name
Test status
Simulation time 95811230 ps
CPU time 1.34 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:51 PM PDT 24
Peak memory 215056 kb
Host smart-f4b3b4dd-a0b4-40ec-9eff-47a0447e308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381911995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.2381911995
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.2800327077
Short name T228
Test name
Test status
Simulation time 30612734 ps
CPU time 1.11 seconds
Started Jun 24 06:30:49 PM PDT 24
Finished Jun 24 06:30:51 PM PDT 24
Peak memory 219488 kb
Host smart-859590e0-b433-4b11-9cc3-12737e950014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800327077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2800327077
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1169048599
Short name T947
Test name
Test status
Simulation time 104835436 ps
CPU time 0.93 seconds
Started Jun 24 06:30:50 PM PDT 24
Finished Jun 24 06:30:53 PM PDT 24
Peak memory 216596 kb
Host smart-6b6bc870-2282-4da7-8fd0-d2cc20016040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169048599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1169048599
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.438558785
Short name T558
Test name
Test status
Simulation time 39583924 ps
CPU time 1.14 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:02 PM PDT 24
Peak memory 219368 kb
Host smart-bf863b3f-989a-4a71-b0af-dad09995befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438558785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.438558785
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.1781762107
Short name T148
Test name
Test status
Simulation time 24597882 ps
CPU time 1.13 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 229028 kb
Host smart-447787b8-3ee5-4a79-a044-140be4214c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781762107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1781762107
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3017776390
Short name T417
Test name
Test status
Simulation time 24184336 ps
CPU time 1.16 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 219124 kb
Host smart-633ba0f2-17ca-4351-925e-2cdf1794fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017776390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3017776390
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.784284912
Short name T129
Test name
Test status
Simulation time 33211314 ps
CPU time 1.32 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 215084 kb
Host smart-7a2f40b1-866f-4e5d-bca7-f63d617c336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784284912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.784284912
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.1372119390
Short name T566
Test name
Test status
Simulation time 24459779 ps
CPU time 0.93 seconds
Started Jun 24 06:31:12 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 217600 kb
Host smart-45cc9c56-6c27-4a1e-9de5-2183ce9a85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372119390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1372119390
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.744886905
Short name T542
Test name
Test status
Simulation time 99173087 ps
CPU time 1.5 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 217696 kb
Host smart-969c0c84-05bf-41b8-b407-8258dbe56ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744886905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.744886905
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3873475208
Short name T206
Test name
Test status
Simulation time 20348583 ps
CPU time 1.1 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 217916 kb
Host smart-a8bd819c-2ace-4bc6-8e92-c53643d77295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873475208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3873475208
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2598723170
Short name T425
Test name
Test status
Simulation time 107419929 ps
CPU time 1.28 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 217696 kb
Host smart-a02b2ec1-105f-4f8a-9900-6569f4bef45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598723170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2598723170
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2436202289
Short name T302
Test name
Test status
Simulation time 26688371 ps
CPU time 1.29 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 218260 kb
Host smart-fa0e576e-415d-449c-8458-e72de6fac1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436202289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2436202289
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.3827456010
Short name T142
Test name
Test status
Simulation time 45679414 ps
CPU time 1.06 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 219056 kb
Host smart-e3009a26-805a-4682-98cc-011dc8470f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827456010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3827456010
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.938158427
Short name T550
Test name
Test status
Simulation time 58418997 ps
CPU time 1.17 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 218292 kb
Host smart-9775c8dc-5cee-428f-8a94-e5689e842668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938158427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.938158427
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.439484832
Short name T766
Test name
Test status
Simulation time 101790510 ps
CPU time 1.27 seconds
Started Jun 24 06:30:59 PM PDT 24
Finished Jun 24 06:31:02 PM PDT 24
Peak memory 219144 kb
Host smart-dcf73a74-f426-4295-920d-b4751b17f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439484832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.439484832
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.638511435
Short name T769
Test name
Test status
Simulation time 19131722 ps
CPU time 1.04 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 217928 kb
Host smart-0e2c6c8b-6f2d-4fe3-a5e7-53d6e8bd5d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638511435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.638511435
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1191647966
Short name T856
Test name
Test status
Simulation time 102565077 ps
CPU time 1.48 seconds
Started Jun 24 06:30:57 PM PDT 24
Finished Jun 24 06:31:00 PM PDT 24
Peak memory 218112 kb
Host smart-22d619af-735e-4352-9257-838d8a00447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191647966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1191647966
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.512832402
Short name T862
Test name
Test status
Simulation time 45266430 ps
CPU time 1.18 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 218288 kb
Host smart-4372a49d-de9c-468a-a111-6b63266a7202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512832402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.512832402
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.599389329
Short name T207
Test name
Test status
Simulation time 26260016 ps
CPU time 0.94 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 218904 kb
Host smart-6d9a666b-818c-4245-8ac2-f30e69f6cbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599389329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.599389329
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3211899755
Short name T107
Test name
Test status
Simulation time 229492188 ps
CPU time 2.87 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 216876 kb
Host smart-ec0e9c6e-4d16-48e1-ad95-ba765e2119d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211899755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3211899755
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2886146375
Short name T374
Test name
Test status
Simulation time 39041980 ps
CPU time 1.16 seconds
Started Jun 24 06:29:03 PM PDT 24
Finished Jun 24 06:29:06 PM PDT 24
Peak memory 217908 kb
Host smart-c9246091-fe9b-47a9-bb18-7ac38b92d228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886146375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2886146375
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.981474280
Short name T760
Test name
Test status
Simulation time 15069673 ps
CPU time 0.89 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:55 PM PDT 24
Peak memory 206072 kb
Host smart-2a4f4f74-312c-491e-8de1-01ee62a2ec4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981474280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.981474280
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2936159915
Short name T900
Test name
Test status
Simulation time 27281372 ps
CPU time 0.83 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:54 PM PDT 24
Peak memory 215660 kb
Host smart-f8bebab7-6057-4076-ada4-3b751962e018
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936159915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2936159915
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.680578914
Short name T164
Test name
Test status
Simulation time 91653657 ps
CPU time 1.02 seconds
Started Jun 24 06:28:55 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 216436 kb
Host smart-e5712532-5841-42c8-be3d-14ac1a2ea1c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680578914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.680578914
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3151462559
Short name T514
Test name
Test status
Simulation time 38505668 ps
CPU time 0.94 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 223188 kb
Host smart-4e68f207-9b11-4eb4-90bc-083d5e657bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151462559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3151462559
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1570241334
Short name T373
Test name
Test status
Simulation time 65250911 ps
CPU time 1.47 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 216712 kb
Host smart-592a6b18-d72d-4a98-b322-da296be56cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570241334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1570241334
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2801610486
Short name T6
Test name
Test status
Simulation time 20299161 ps
CPU time 1.09 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 216004 kb
Host smart-81e269d7-3abc-4f65-af86-703f7266e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801610486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2801610486
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1375925435
Short name T697
Test name
Test status
Simulation time 86139702 ps
CPU time 0.95 seconds
Started Jun 24 06:28:45 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 206416 kb
Host smart-b8c5ff6c-5bfe-400e-ae5f-6b9d1c9943d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375925435 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1375925435
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1686923902
Short name T573
Test name
Test status
Simulation time 60207325 ps
CPU time 0.99 seconds
Started Jun 24 06:28:43 PM PDT 24
Finished Jun 24 06:28:45 PM PDT 24
Peak memory 214616 kb
Host smart-f33013ec-1143-4c7f-aed5-70e2655ffe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686923902 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1686923902
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2198460574
Short name T606
Test name
Test status
Simulation time 282566388 ps
CPU time 2.09 seconds
Started Jun 24 06:28:44 PM PDT 24
Finished Jun 24 06:28:48 PM PDT 24
Peak memory 214644 kb
Host smart-f70b310e-1c7f-4cda-bf17-0c12bdd86268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198460574 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2198460574
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1955848230
Short name T752
Test name
Test status
Simulation time 41864199619 ps
CPU time 446.16 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:36:21 PM PDT 24
Peak memory 222928 kb
Host smart-21a48bf3-0b61-47b7-86a5-e89161e2016c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955848230 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1955848230
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.2936338902
Short name T504
Test name
Test status
Simulation time 28464037 ps
CPU time 1.32 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 219212 kb
Host smart-d8c97b67-0640-49f3-9a3b-67000b731926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936338902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.2936338902
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.1453569001
Short name T149
Test name
Test status
Simulation time 24557598 ps
CPU time 1.07 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 229000 kb
Host smart-292b0b4b-0c9f-4ab0-9e23-f8d839676ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453569001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1453569001
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3216917875
Short name T338
Test name
Test status
Simulation time 48266365 ps
CPU time 1.73 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 217784 kb
Host smart-152a577b-a634-4f4c-9d2c-0a1fe22c708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216917875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3216917875
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1690067830
Short name T139
Test name
Test status
Simulation time 50323649 ps
CPU time 1.2 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 217880 kb
Host smart-0e599de5-b606-4a80-b7df-4596586914b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690067830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1690067830
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2058425128
Short name T865
Test name
Test status
Simulation time 97977325 ps
CPU time 1.25 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 219080 kb
Host smart-bcb47ac7-959a-4ffa-8ada-93412dcc45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058425128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2058425128
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1499858175
Short name T14
Test name
Test status
Simulation time 33033541 ps
CPU time 1.39 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 219256 kb
Host smart-952cd66e-7865-4914-9931-083bb68cf6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499858175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1499858175
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2802644546
Short name T2
Test name
Test status
Simulation time 30327287 ps
CPU time 1.35 seconds
Started Jun 24 06:31:09 PM PDT 24
Finished Jun 24 06:31:11 PM PDT 24
Peak memory 219648 kb
Host smart-9ff3aa72-525b-49b0-8d6b-4697db00f8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802644546 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2802644546
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1360583855
Short name T898
Test name
Test status
Simulation time 20535493 ps
CPU time 1.24 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 229128 kb
Host smart-bb8a41fc-ac3f-44e5-8236-ab365d5eddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360583855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1360583855
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1117912199
Short name T93
Test name
Test status
Simulation time 40337826 ps
CPU time 1.54 seconds
Started Jun 24 06:31:03 PM PDT 24
Finished Jun 24 06:31:06 PM PDT 24
Peak memory 216636 kb
Host smart-2adcdafc-3b74-47ef-8da6-bca77de029fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117912199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1117912199
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.2758777868
Short name T978
Test name
Test status
Simulation time 29259178 ps
CPU time 1.34 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 217964 kb
Host smart-c7b098da-8b48-49be-99b9-280097f79b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758777868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2758777868
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.703825380
Short name T253
Test name
Test status
Simulation time 27056260 ps
CPU time 1.13 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 219404 kb
Host smart-d7109ed5-6548-45a6-a19e-76f6babc3eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703825380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.703825380
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_alert.1663144513
Short name T544
Test name
Test status
Simulation time 53450772 ps
CPU time 1.19 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:05 PM PDT 24
Peak memory 219056 kb
Host smart-a9a51ee8-5947-461c-9119-999d2ac0c244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663144513 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1663144513
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.4162060261
Short name T565
Test name
Test status
Simulation time 19582626 ps
CPU time 1.04 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 218900 kb
Host smart-fbfa9380-d739-4be3-9813-8931c3964eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162060261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4162060261
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3595130770
Short name T84
Test name
Test status
Simulation time 27981639 ps
CPU time 1.28 seconds
Started Jun 24 06:31:02 PM PDT 24
Finished Jun 24 06:31:06 PM PDT 24
Peak memory 217872 kb
Host smart-23d587f4-e081-487b-b7ce-fe2b3b15f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595130770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3595130770
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.3577789706
Short name T167
Test name
Test status
Simulation time 30235998 ps
CPU time 1.27 seconds
Started Jun 24 06:31:01 PM PDT 24
Finished Jun 24 06:31:04 PM PDT 24
Peak memory 218816 kb
Host smart-ec425536-141b-4d76-83d8-adfbcdc38768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577789706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.3577789706
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.1882978427
Short name T140
Test name
Test status
Simulation time 21164240 ps
CPU time 1.19 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 228992 kb
Host smart-889c9ee4-3cea-4a5e-909f-decbb8f9eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882978427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1882978427
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3459137011
Short name T884
Test name
Test status
Simulation time 92164358 ps
CPU time 1.35 seconds
Started Jun 24 06:31:00 PM PDT 24
Finished Jun 24 06:31:03 PM PDT 24
Peak memory 218064 kb
Host smart-81ceae6f-26fa-472c-8d1c-12bfcc15f7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459137011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3459137011
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.223991531
Short name T493
Test name
Test status
Simulation time 38108014 ps
CPU time 1.11 seconds
Started Jun 24 06:31:12 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 218128 kb
Host smart-6d055096-4d9d-45d8-90c7-726cd22e4574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223991531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.223991531
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.211367171
Short name T224
Test name
Test status
Simulation time 19808867 ps
CPU time 1.07 seconds
Started Jun 24 06:31:15 PM PDT 24
Finished Jun 24 06:31:17 PM PDT 24
Peak memory 218016 kb
Host smart-487b405a-3c72-4f83-975f-fdb7eb4847cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211367171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.211367171
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.528442623
Short name T99
Test name
Test status
Simulation time 41055667 ps
CPU time 1.52 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 217844 kb
Host smart-e75bfb48-d107-431f-ba84-233eeedf6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528442623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.528442623
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2737646214
Short name T948
Test name
Test status
Simulation time 89315731 ps
CPU time 1.23 seconds
Started Jun 24 06:31:09 PM PDT 24
Finished Jun 24 06:31:11 PM PDT 24
Peak memory 217820 kb
Host smart-409d447f-bb70-405a-931c-4e97d3693910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737646214 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2737646214
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.970764188
Short name T778
Test name
Test status
Simulation time 17741376 ps
CPU time 1.02 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:12 PM PDT 24
Peak memory 217800 kb
Host smart-1a007a7a-7c77-49e3-8dd0-869acb480140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970764188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.970764188
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1308175696
Short name T332
Test name
Test status
Simulation time 65346303 ps
CPU time 1.27 seconds
Started Jun 24 06:31:09 PM PDT 24
Finished Jun 24 06:31:12 PM PDT 24
Peak memory 218236 kb
Host smart-d5523bdb-8e97-4bcf-993a-8fc7957199d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308175696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1308175696
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.3945789830
Short name T924
Test name
Test status
Simulation time 21235667 ps
CPU time 1.12 seconds
Started Jun 24 06:31:12 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 218988 kb
Host smart-3d37b50d-1626-4d2d-a977-103b6edebcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945789830 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.3945789830
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.318948834
Short name T232
Test name
Test status
Simulation time 22869535 ps
CPU time 1.06 seconds
Started Jun 24 06:31:15 PM PDT 24
Finished Jun 24 06:31:18 PM PDT 24
Peak memory 228980 kb
Host smart-42f9e24d-2483-45eb-a0a7-5c4776214140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318948834 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.318948834
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1866891372
Short name T3
Test name
Test status
Simulation time 45743054 ps
CPU time 1.58 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 218064 kb
Host smart-a4d54de0-caa5-454b-8107-a7bab246ce31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866891372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1866891372
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.1677473037
Short name T764
Test name
Test status
Simulation time 50979085 ps
CPU time 1.19 seconds
Started Jun 24 06:31:12 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 219008 kb
Host smart-db170240-4c12-4087-9f18-5f11bb373a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677473037 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.1677473037
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.1247040175
Short name T472
Test name
Test status
Simulation time 21661730 ps
CPU time 1.15 seconds
Started Jun 24 06:31:09 PM PDT 24
Finished Jun 24 06:31:12 PM PDT 24
Peak memory 228948 kb
Host smart-2e3d75ae-808d-4a74-94ba-43f4620e6bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247040175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1247040175
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3715221833
Short name T404
Test name
Test status
Simulation time 152360530 ps
CPU time 1.16 seconds
Started Jun 24 06:31:15 PM PDT 24
Finished Jun 24 06:31:18 PM PDT 24
Peak memory 216600 kb
Host smart-dccd0cdb-92aa-4283-bb05-2b3f0c8464b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715221833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3715221833
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.770353932
Short name T77
Test name
Test status
Simulation time 32409896 ps
CPU time 0.83 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:55 PM PDT 24
Peak memory 205700 kb
Host smart-ead6526d-18ca-4b5a-913d-7f2097bf508c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770353932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.770353932
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.409742729
Short name T227
Test name
Test status
Simulation time 20426788 ps
CPU time 0.88 seconds
Started Jun 24 06:28:53 PM PDT 24
Finished Jun 24 06:28:54 PM PDT 24
Peak memory 215684 kb
Host smart-81bb29cd-3539-46fa-97f3-64bbf46c31e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409742729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.409742729
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2181393747
Short name T22
Test name
Test status
Simulation time 45481500 ps
CPU time 1.42 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 216256 kb
Host smart-df3a399f-3173-4c75-871e-be8ca6194b12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181393747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2181393747
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3777929604
Short name T177
Test name
Test status
Simulation time 30289567 ps
CPU time 1.28 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 219036 kb
Host smart-84cbec0c-efb4-4431-bce1-581f26974200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777929604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3777929604
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.737047567
Short name T604
Test name
Test status
Simulation time 53846424 ps
CPU time 1.04 seconds
Started Jun 24 06:28:52 PM PDT 24
Finished Jun 24 06:28:54 PM PDT 24
Peak memory 216644 kb
Host smart-b24eb25f-636b-44dc-9f10-ebf2173915ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737047567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.737047567
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3660894297
Short name T110
Test name
Test status
Simulation time 20009388 ps
CPU time 1.09 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:28:56 PM PDT 24
Peak memory 215040 kb
Host smart-0a5ee1d5-edea-42a5-847b-f1d23da82d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660894297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3660894297
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.154715174
Short name T26
Test name
Test status
Simulation time 39129037 ps
CPU time 0.91 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:03 PM PDT 24
Peak memory 206420 kb
Host smart-edbb4c83-ca17-4611-8af0-f544178213c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154715174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.154715174
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3111731300
Short name T598
Test name
Test status
Simulation time 21651987 ps
CPU time 0.86 seconds
Started Jun 24 06:29:01 PM PDT 24
Finished Jun 24 06:29:04 PM PDT 24
Peak memory 214604 kb
Host smart-98d2d25a-733b-42db-b940-3fabfbfc9b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111731300 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3111731300
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.224001002
Short name T5
Test name
Test status
Simulation time 554328768 ps
CPU time 6.06 seconds
Started Jun 24 06:28:56 PM PDT 24
Finished Jun 24 06:29:03 PM PDT 24
Peak memory 216620 kb
Host smart-9bc8588f-d8a0-4c8b-b411-5c920fedf53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224001002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.224001002
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.462533501
Short name T245
Test name
Test status
Simulation time 285525396927 ps
CPU time 1684.51 seconds
Started Jun 24 06:28:54 PM PDT 24
Finished Jun 24 06:57:00 PM PDT 24
Peak memory 223912 kb
Host smart-9995182b-8ef8-490a-8951-441186869ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462533501 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.462533501
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_alert.2076937361
Short name T825
Test name
Test status
Simulation time 160051619 ps
CPU time 1.18 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:12 PM PDT 24
Peak memory 218316 kb
Host smart-f5b7af6f-11f7-4dc3-be5c-5fee8b01489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076937361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.2076937361
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.4169316990
Short name T397
Test name
Test status
Simulation time 30055836 ps
CPU time 1.28 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 219524 kb
Host smart-0df26f53-5488-49f9-be93-85cf67076712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169316990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4169316990
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3479003270
Short name T333
Test name
Test status
Simulation time 73979444 ps
CPU time 1.34 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 218272 kb
Host smart-9a7a94fb-9e49-4114-8553-b6bcad254d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479003270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3479003270
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.3280829117
Short name T721
Test name
Test status
Simulation time 70001947 ps
CPU time 1.36 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 217708 kb
Host smart-1f70ddae-df1b-411c-a155-6b2f75a1dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280829117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.3280829117
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.4102477095
Short name T968
Test name
Test status
Simulation time 33219142 ps
CPU time 0.98 seconds
Started Jun 24 06:31:15 PM PDT 24
Finished Jun 24 06:31:18 PM PDT 24
Peak memory 219224 kb
Host smart-2ab61cc2-db1e-4fd3-b1d1-b94b93610297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102477095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.4102477095
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3007299704
Short name T541
Test name
Test status
Simulation time 58098592 ps
CPU time 1.16 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 219176 kb
Host smart-e505756c-baf6-4bb3-82e2-46c34f4944b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007299704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3007299704
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.2560515485
Short name T287
Test name
Test status
Simulation time 95998558 ps
CPU time 1.25 seconds
Started Jun 24 06:31:13 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 218944 kb
Host smart-c5d89fe3-0407-4582-938c-0d3700a84ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560515485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.2560515485
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.1783956955
Short name T132
Test name
Test status
Simulation time 33625582 ps
CPU time 1.05 seconds
Started Jun 24 06:31:12 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 229100 kb
Host smart-67e5d6a8-30d7-4743-97d1-f61eeffb0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783956955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1783956955
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.497855299
Short name T455
Test name
Test status
Simulation time 23557092 ps
CPU time 1.15 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 216640 kb
Host smart-f9b587e3-44fe-48bf-bdff-c3dcc9cd784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497855299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.497855299
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.3938530609
Short name T434
Test name
Test status
Simulation time 24656339 ps
CPU time 1.22 seconds
Started Jun 24 06:31:13 PM PDT 24
Finished Jun 24 06:31:16 PM PDT 24
Peak memory 219224 kb
Host smart-cde50f8c-0308-4cdd-a737-3afb094bc364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938530609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.3938530609
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3750055546
Short name T412
Test name
Test status
Simulation time 44030844 ps
CPU time 0.98 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 218020 kb
Host smart-d3482fba-2cfb-47b0-bf99-e5276616e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750055546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3750055546
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4031843097
Short name T13
Test name
Test status
Simulation time 42165749 ps
CPU time 1.63 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 214616 kb
Host smart-08a25b8b-2cbe-4514-913b-fa78ec3ae018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031843097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4031843097
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.3587377098
Short name T653
Test name
Test status
Simulation time 151109328 ps
CPU time 1.3 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 219044 kb
Host smart-374f6457-25ee-42c3-961e-f61d1c92d22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587377098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.3587377098
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.205944776
Short name T61
Test name
Test status
Simulation time 31889686 ps
CPU time 1.02 seconds
Started Jun 24 06:31:16 PM PDT 24
Finished Jun 24 06:31:18 PM PDT 24
Peak memory 218040 kb
Host smart-d32437a7-ff57-4511-838f-7537df225a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205944776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.205944776
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3318466361
Short name T906
Test name
Test status
Simulation time 194394328 ps
CPU time 1.36 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:12 PM PDT 24
Peak memory 219268 kb
Host smart-2db62879-41e7-4fac-bd92-8ad100c25413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318466361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3318466361
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.2132110666
Short name T204
Test name
Test status
Simulation time 43113093 ps
CPU time 1.16 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 218644 kb
Host smart-15bd7cbd-320e-4f85-b8e9-b8dc8750cc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132110666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.2132110666
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.1732480258
Short name T199
Test name
Test status
Simulation time 24085336 ps
CPU time 1.1 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 223612 kb
Host smart-a7f39c10-ce30-4e6a-bf4b-2729be332539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732480258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1732480258
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1041162384
Short name T792
Test name
Test status
Simulation time 75063981 ps
CPU time 1.11 seconds
Started Jun 24 06:31:09 PM PDT 24
Finished Jun 24 06:31:11 PM PDT 24
Peak memory 219472 kb
Host smart-9874e939-3c93-40d2-9a5b-8ba27e952d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041162384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1041162384
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.3664132628
Short name T643
Test name
Test status
Simulation time 57396847 ps
CPU time 1.22 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 220680 kb
Host smart-d8fe1776-1955-490d-856c-dab294aa20d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664132628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.3664132628
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2547583334
Short name T777
Test name
Test status
Simulation time 29721402 ps
CPU time 1 seconds
Started Jun 24 06:31:13 PM PDT 24
Finished Jun 24 06:31:15 PM PDT 24
Peak memory 223380 kb
Host smart-546e85a2-439f-443a-86ae-3e7f62ff8391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547583334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2547583334
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2729201416
Short name T836
Test name
Test status
Simulation time 54879230 ps
CPU time 1.37 seconds
Started Jun 24 06:31:13 PM PDT 24
Finished Jun 24 06:31:17 PM PDT 24
Peak memory 218200 kb
Host smart-d598bff1-cf9c-475f-a2fe-b47434febe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729201416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2729201416
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2130900148
Short name T250
Test name
Test status
Simulation time 33088674 ps
CPU time 1.33 seconds
Started Jun 24 06:31:15 PM PDT 24
Finished Jun 24 06:31:18 PM PDT 24
Peak memory 215080 kb
Host smart-2c56b503-d0d0-4139-8544-b52ea68e0df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130900148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2130900148
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.1041931791
Short name T726
Test name
Test status
Simulation time 33092637 ps
CPU time 0.88 seconds
Started Jun 24 06:31:14 PM PDT 24
Finished Jun 24 06:31:17 PM PDT 24
Peak memory 218904 kb
Host smart-666b6019-e1d6-432e-84ac-c5d1be9b6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041931791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1041931791
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1763077674
Short name T958
Test name
Test status
Simulation time 82310317 ps
CPU time 1 seconds
Started Jun 24 06:31:10 PM PDT 24
Finished Jun 24 06:31:13 PM PDT 24
Peak memory 216752 kb
Host smart-efa48b37-7f1e-4736-9580-775801b0f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763077674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1763077674
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.70986044
Short name T588
Test name
Test status
Simulation time 71928085 ps
CPU time 1.16 seconds
Started Jun 24 06:31:16 PM PDT 24
Finished Jun 24 06:31:19 PM PDT 24
Peak memory 218960 kb
Host smart-60acf7f3-a7f0-40dc-812f-62c0a3212c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70986044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.70986044
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.2457834958
Short name T175
Test name
Test status
Simulation time 20362457 ps
CPU time 1.08 seconds
Started Jun 24 06:31:21 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 217844 kb
Host smart-ed121784-38d7-40b3-86e1-c9cd743e4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457834958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2457834958
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2072333028
Short name T463
Test name
Test status
Simulation time 168617758 ps
CPU time 1.08 seconds
Started Jun 24 06:31:11 PM PDT 24
Finished Jun 24 06:31:14 PM PDT 24
Peak memory 216696 kb
Host smart-f9d32d9e-2af9-46f1-b328-947a7503ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072333028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2072333028
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.2518549392
Short name T400
Test name
Test status
Simulation time 27822086 ps
CPU time 1.27 seconds
Started Jun 24 06:31:18 PM PDT 24
Finished Jun 24 06:31:22 PM PDT 24
Peak memory 219080 kb
Host smart-a693a885-c80e-4774-9b93-730debabaa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518549392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.2518549392
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.2735117853
Short name T59
Test name
Test status
Simulation time 24088741 ps
CPU time 0.97 seconds
Started Jun 24 06:31:21 PM PDT 24
Finished Jun 24 06:31:25 PM PDT 24
Peak memory 217532 kb
Host smart-19c53e3f-12a0-45e3-9617-67f124b79fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735117853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2735117853
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2537227870
Short name T949
Test name
Test status
Simulation time 47468258 ps
CPU time 1.85 seconds
Started Jun 24 06:31:22 PM PDT 24
Finished Jun 24 06:31:27 PM PDT 24
Peak memory 214508 kb
Host smart-02e8c538-7326-4706-afe2-14630c95b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537227870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2537227870
Directory /workspace/99.edn_genbits/latest
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