Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cs_cmds_cg

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cs_cmds_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cs_cmds_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cs_cmds_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	34	0	34	100.00

Variables for Group Instance edn_cs_cmds_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acmd	5	0	5	100.00	100	1	1	0
cp_clen	2	0	2	100.00	100	1	1	0
cp_cmd_src	5	0	5	100.00	100	1	1	0
cp_flags	2	0	2	100.00	100	1	1	0
cp_glen	2	0	2	100.00	100	1	1	0
cp_mode	3	0	3	100.00	100	1	1	0

Crosses for Group Instance edn_cs_cmds_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_generate_intended	9	0	9	100.00	100	1	1	0
cr_instantiate_intended	9	0	9	100.00	100	1	1	0
cr_reseed_intended	8	0	8	100.00	100	1	1	0
cr_update_intended	2	0	2	100.00	100	1	1	0
cr_uninstantiate_intended	1	0	1	100.00	100	1	1	0
cr_acmd_mode_cmd_src_unintended	5	0	5	100.00	100	1	1	0

Summary for Variable cp_acmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_acmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[INV]	0	Excluded
auto[GENB]	0	Excluded
auto[GENU]	0	Excluded
unused	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[INS]	4424	1			T1	1		T2	1		T3	2
auto[RES]	1125	1			T5	1		T26	1		T10	2
auto[GEN]	4509	1			T1	1		T2	1		T3	2
auto[UPD]	555	1			T3	1		T6	2		T35	1
auto[UNI]	3624	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_clen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_clen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

some_cmd_data

4628

1

T3

2

T26

3

T10

3

no_cmd_data

9615

1

T1

3

T2

3

T3

4

---

Summary for Variable cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_cmd_src

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_cmd_req	12396	1			T1	3		T2	3		T3	4
reseed_cmd	594	1			T5	1		T10	2		T11	2
generate_cmd	546	1			T5	1		T10	2		T11	2
boot_gen_cmd	403	1			T3	1		T23	1		T5	2
boot_ins_cmd	304	1			T3	1		T5	2		T33	1

---

Summary for Variable cp_flags

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_flags

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

true

4761

1

T2

1

T3

2

T23

3

false

9482

1

T1

3

T2

2

T3

4

---

Summary for Variable cp_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_glen

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

1412

1

T3

1

T5

2

T26

2

one

2668

1

T1

1

T2

1

T3

3

---

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_mode	11421	1			T1	3		T2	3		T3	4
boot_mode	781	1			T3	2		T23	1		T5	6
auto_mode	2041	1			T23	3		T10	6		T11	6

---

Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_glen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_glen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[GEN]

some_cmd_data

multiple

sw_mode

sw_cmd_req

178

1

T26

1

T34

1

T91

1

auto[GEN]

some_cmd_data

multiple

auto_mode

generate_cmd

123

1

T10

2

T12

1

T21

2

auto[GEN]

some_cmd_data

one

sw_mode

sw_cmd_req

62

1

T3

1

T96

1

T83

1

auto[GEN]

some_cmd_data

one

auto_mode

generate_cmd

146

1

T11

1

T29

1

T30

1

auto[GEN]

no_cmd_data

multiple

sw_mode

sw_cmd_req

46

1

T35

1

T36

1

T49

1

auto[GEN]

no_cmd_data

multiple

boot_mode

boot_gen_cmd

66

1

T34

1

T49

1

T51

1

auto[GEN]

no_cmd_data

multiple

auto_mode

generate_cmd

30

1

T12

1

T113

1

T85

1

auto[GEN]

no_cmd_data

one

sw_mode

sw_cmd_req

1487

1

T1

1

T2

1

T4

1

auto[GEN]

no_cmd_data

one

auto_mode

generate_cmd

195

1

T11

1

T31

1

T22

2

User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_gen	0	Excluded
gen_auto_wrong_src	0	Excluded
gen_boot_wrong_src	0	Excluded
gen_boot_seq_wrong_clen	0	Excluded
gen_boot_seq_wrong_glen	0	Excluded
gen_sw_wrong_src	0	Excluded

---

Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	9	0	9	100.00
Automatically Generated Cross Bins	9	0	9	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

some_cmd_data

true

sw_mode

sw_cmd_req

875

1

T26

1

T6

3

T35

1

auto[INS]

some_cmd_data

true

auto_mode

sw_cmd_req

81

1

T10

1

T12

1

T21

1

auto[INS]

some_cmd_data

false

sw_mode

sw_cmd_req

832

1

T6

9

T34

1

T36

1

auto[INS]

some_cmd_data

false

auto_mode

sw_cmd_req

69

1

T11

2

T12

1

T85

1

auto[INS]

no_cmd_data

true

sw_mode

sw_cmd_req

209

1

T6

2

T47

2

T48

6

auto[INS]

no_cmd_data

true

auto_mode

sw_cmd_req

226

1

T23

1

T29

1

T30

1

auto[INS]

no_cmd_data

false

sw_mode

sw_cmd_req

1671

1

T1

1

T2

1

T3

1

auto[INS]

no_cmd_data

false

boot_mode

boot_ins_cmd

140

1

T5

2

T50

1

T174

1

auto[INS]

no_cmd_data

false

auto_mode

sw_cmd_req

157

1

T10

1

T21

1

T31

1

User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_ins	0	Excluded
ins_auto_wrong_src	0	Excluded
ins_boot_wrong_src	0	Excluded
ins_boot_seq_wrong_clen	0	Excluded
ins_boot_seq_wrong_flag0	0	Excluded
ins_sw_wrong_src	0	Excluded

---

Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	8	0	8	100.00
Automatically Generated Cross Bins	8	0	8	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[RES]

some_cmd_data

true

sw_mode

sw_cmd_req

188

1

T6

1

T47

1

T48

2

auto[RES]

some_cmd_data

true

auto_mode

reseed_cmd

135

1

T12

1

T21

1

T22

1

auto[RES]

some_cmd_data

false

sw_mode

sw_cmd_req

218

1

T26

1

T6

3

T34

1

auto[RES]

some_cmd_data

false

auto_mode

reseed_cmd

144

1

T11

2

T12

1

T30

1

auto[RES]

no_cmd_data

true

sw_mode

sw_cmd_req

57

1

T47

1

T48

1

T106

1

auto[RES]

no_cmd_data

true

auto_mode

reseed_cmd

38

1

T10

2

T31

1

T32

1

auto[RES]

no_cmd_data

false

sw_mode

sw_cmd_req

58

1

T91

1

T48

1

T54

1

auto[RES]

no_cmd_data

false

auto_mode

reseed_cmd

225

1

T29

1

T31

1

T22

1

User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_res	0	Excluded
res_auto_wrong_src	0	Excluded
res_boot_wrong_src	0	Excluded
res_sw_wrong_src	0	Excluded

---

Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins

cp_acmd	cp_clen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)

Covered bins

cp_acmd

cp_clen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UPD]

some_cmd_data

sw_mode

sw_cmd_req

433

1

T3

1

T6

1

T35

1

auto[UPD]

no_cmd_data

sw_mode

sw_cmd_req

105

1

T6

1

T47

2

T48

2

User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_upd	0	Excluded
upd_auto_wrong_src	0	Excluded
upd_boot_wrong_src	0	Excluded
upd_sw_wrong_src	0	Excluded

---

Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	1	0	1	100.00
Automatically Generated Cross Bins	1	0	1	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UNI]

sw_mode

sw_cmd_req

3605

1

T1

1

T2

1

T3

1

User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_uni	0	Excluded
uni_auto_wrong_src	0	Excluded
uni_boot_wrong_src	0	Excluded
uni_sw_wrong_src	0	Excluded

---

Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	0	5	100.00
Automatically Generated Cross Bins	5	0	5	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

auto_mode

sw_cmd_req

533

1

T23

1

T10

2

T11

2

auto[RES]

auto_mode

sw_cmd_req

10

1

T14

1

T354

1

T355

1

auto[GEN]

auto_mode

sw_cmd_req

420

1

T23

2

T29

2

T30

2

auto[UPD]

auto_mode

sw_cmd_req

17

1

T82

1

T69

1

T356

1

auto[UNI]

auto_mode

sw_cmd_req

19

1

T83

1

T339

1

T331

1

User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_sw_cmd	0	Excluded
not_auto_mode	0	Excluded