Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5049489

1

T1

9

T2

14

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1514746	1			T1	53		T2	21		T3	47
values[0x0]	1931888	1			T1	5		T2	7		T3	18
values[0x1]	2245894	1			T1	4		T2	3		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	321598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5370930

1

T1

27

T2

19

T3

46

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22112	1			T25	1		T6	29		T47	76
valid_sources[0x01]	22589	1			T10	4		T6	301		T37	1
valid_sources[0x02]	23169	1			T6	144		T47	98		T48	317
valid_sources[0x03]	22277	1			T6	519		T33	1		T29	6
valid_sources[0x04]	23006	1			T26	6		T6	449		T33	1
valid_sources[0x05]	23143	1			T23	3		T6	118		T47	88
valid_sources[0x06]	22797	1			T26	1		T6	95		T47	96
valid_sources[0x07]	21313	1			T25	2		T6	364		T50	1
valid_sources[0x08]	21816	1			T6	414		T37	2		T47	95
valid_sources[0x09]	21973	1			T6	275		T91	1		T47	104
valid_sources[0x0a]	21556	1			T23	1		T24	1		T26	3
valid_sources[0x0b]	21936	1			T6	33		T37	1		T96	7
valid_sources[0x0c]	22643	1			T6	18		T12	1		T91	1
valid_sources[0x0d]	21699	1			T26	9		T6	312		T12	1
valid_sources[0x0e]	21080	1			T26	1		T6	423		T12	1
valid_sources[0x0f]	22356	1			T6	6		T91	1		T16	2
valid_sources[0x10]	22568	1			T6	227		T12	1		T96	1
valid_sources[0x11]	22388	1			T26	5		T6	398		T12	2
valid_sources[0x12]	23681	1			T23	2		T6	25		T35	2
valid_sources[0x13]	21139	1			T6	63		T91	2		T47	83
valid_sources[0x14]	22415	1			T25	2		T6	158		T96	1
valid_sources[0x15]	21630	1			T23	2		T26	5		T6	393
valid_sources[0x16]	21285	1			T6	22		T16	1		T47	82
valid_sources[0x17]	22799	1			T23	1		T26	1		T10	4
valid_sources[0x18]	22030	1			T26	13		T6	60		T12	1
valid_sources[0x19]	22866	1			T25	1		T6	121		T12	5
valid_sources[0x1a]	22573	1			T26	7		T6	245		T90	4
valid_sources[0x1b]	23656	1			T6	783		T91	1		T96	1
valid_sources[0x1c]	21625	1			T23	1		T25	1		T6	14
valid_sources[0x1d]	21492	1			T6	115		T91	1		T96	2
valid_sources[0x1e]	22752	1			T23	2		T26	2		T6	129
valid_sources[0x1f]	21826	1			T5	3		T6	95		T37	2
valid_sources[0x20]	23069	1			T23	1		T6	417		T90	1
valid_sources[0x21]	21918	1			T23	1		T6	439		T12	4
valid_sources[0x22]	21526	1			T26	1		T6	23		T96	1
valid_sources[0x23]	22647	1			T25	1		T26	1		T6	98
valid_sources[0x24]	21022	1			T26	1		T6	13		T90	1
valid_sources[0x25]	22227	1			T6	239		T37	1		T91	2
valid_sources[0x26]	21757	1			T26	6		T6	327		T12	1
valid_sources[0x27]	20775	1			T6	57		T35	10		T91	1
valid_sources[0x28]	20747	1			T23	2		T6	193		T12	1
valid_sources[0x29]	24004	1			T23	1		T6	148		T91	1
valid_sources[0x2a]	23666	1			T24	1		T26	2		T6	316
valid_sources[0x2b]	24139	1			T25	2		T26	1		T6	12
valid_sources[0x2c]	22473	1			T25	1		T26	2		T6	50
valid_sources[0x2d]	21716	1			T6	15		T37	2		T47	83
valid_sources[0x2e]	22238	1			T5	1		T6	208		T47	89
valid_sources[0x2f]	22829	1			T4	26		T26	1		T6	144
valid_sources[0x30]	22467	1			T6	33		T91	1		T47	110
valid_sources[0x31]	20370	1			T5	1		T24	3		T6	34
valid_sources[0x32]	22009	1			T6	17		T47	90		T48	332
valid_sources[0x33]	21807	1			T23	2		T26	9		T6	17
valid_sources[0x34]	22285	1			T23	1		T25	1		T6	16
valid_sources[0x35]	22509	1			T6	55		T91	1		T47	90
valid_sources[0x36]	22656	1			T6	160		T29	6		T90	3
valid_sources[0x37]	21184	1			T6	219		T12	1		T91	1
valid_sources[0x38]	23550	1			T6	269		T11	40		T90	2
valid_sources[0x39]	21766	1			T6	20		T47	126		T44	1
valid_sources[0x3a]	22399	1			T26	1		T6	261		T37	2
valid_sources[0x3b]	22331	1			T6	687		T96	1		T47	113
valid_sources[0x3c]	21699	1			T24	1		T6	155		T47	90
valid_sources[0x3d]	21183	1			T6	84		T47	79		T48	343
valid_sources[0x3e]	21735	1			T6	183		T90	2		T91	1
valid_sources[0x3f]	21416	1			T23	2		T25	1		T6	30
valid_sources[0x40]	24483	1			T26	3		T6	415		T47	101
valid_sources[0x41]	23320	1			T26	3		T6	28		T91	1
valid_sources[0x42]	21457	1			T23	2		T6	132		T29	1
valid_sources[0x43]	22350	1			T6	21		T34	140		T35	16
valid_sources[0x44]	23926	1			T6	395		T12	1		T91	1
valid_sources[0x45]	20813	1			T6	245		T91	3		T47	86
valid_sources[0x46]	21467	1			T6	215		T12	1		T91	1
valid_sources[0x47]	21959	1			T26	2		T6	30		T12	1
valid_sources[0x48]	22814	1			T23	1		T26	1		T6	266
valid_sources[0x49]	22283	1			T26	1		T6	54		T91	1
valid_sources[0x4a]	21441	1			T6	53		T12	3		T47	104
valid_sources[0x4b]	22137	1			T6	286		T29	1		T91	1
valid_sources[0x4c]	19907	1			T10	8		T6	11		T90	1
valid_sources[0x4d]	23655	1			T23	1		T6	10		T90	1
valid_sources[0x4e]	21838	1			T23	1		T26	4		T6	284
valid_sources[0x4f]	22645	1			T24	2		T26	6		T6	128
valid_sources[0x50]	23006	1			T6	185		T50	2		T47	99
valid_sources[0x51]	22692	1			T26	10		T6	344		T90	2
valid_sources[0x52]	22454	1			T26	1		T6	265		T12	2
valid_sources[0x53]	21538	1			T6	122		T91	2		T47	87
valid_sources[0x54]	22277	1			T6	352		T47	96		T44	1
valid_sources[0x55]	22236	1			T26	2		T6	337		T47	88
valid_sources[0x56]	20899	1			T23	1		T6	678		T91	1
valid_sources[0x57]	21346	1			T6	144		T91	1		T47	93
valid_sources[0x58]	22420	1			T6	17		T91	2		T47	97
valid_sources[0x59]	23313	1			T6	201		T90	2		T47	93
valid_sources[0x5a]	21338	1			T24	1		T26	4		T6	681
valid_sources[0x5b]	22260	1			T6	30		T29	1		T96	1
valid_sources[0x5c]	20965	1			T26	1		T6	115		T91	1
valid_sources[0x5d]	22649	1			T23	3		T26	3		T6	359
valid_sources[0x5e]	21015	1			T23	3		T24	1		T26	2
valid_sources[0x5f]	21364	1			T6	342		T12	2		T37	1
valid_sources[0x60]	22718	1			T6	17		T90	7		T91	1
valid_sources[0x61]	23095	1			T5	2		T24	1		T6	306
valid_sources[0x62]	21266	1			T26	6		T6	86		T29	2
valid_sources[0x63]	21220	1			T3	18		T26	5		T6	269
valid_sources[0x64]	22008	1			T24	3		T6	282		T12	2
valid_sources[0x65]	22976	1			T26	7		T6	307		T47	77
valid_sources[0x66]	21513	1			T26	2		T6	148		T91	1
valid_sources[0x67]	23951	1			T6	113		T37	1		T47	99
valid_sources[0x68]	22590	1			T6	92		T35	5		T47	98
valid_sources[0x69]	21080	1			T6	95		T47	92		T48	283
valid_sources[0x6a]	22092	1			T26	3		T6	206		T12	1
valid_sources[0x6b]	22400	1			T6	266		T37	2		T90	2
valid_sources[0x6c]	20796	1			T23	2		T6	91		T47	80
valid_sources[0x6d]	20915	1			T6	107		T12	1		T47	67
valid_sources[0x6e]	21368	1			T6	268		T35	4		T91	1
valid_sources[0x6f]	22064	1			T6	78		T76	1		T47	91
valid_sources[0x70]	22891	1			T6	319		T96	2		T47	90
valid_sources[0x71]	21579	1			T26	1		T6	284		T12	2
valid_sources[0x72]	22965	1			T23	1		T26	2		T6	42
valid_sources[0x73]	22730	1			T26	1		T6	232		T12	2
valid_sources[0x74]	21939	1			T10	23		T6	135		T12	1
valid_sources[0x75]	22003	1			T26	5		T6	364		T16	2
valid_sources[0x76]	22743	1			T24	2		T26	1		T6	333
valid_sources[0x77]	22149	1			T23	1		T6	249		T29	1
valid_sources[0x78]	21949	1			T6	122		T90	1		T91	1
valid_sources[0x79]	21406	1			T6	87		T91	1		T16	1
valid_sources[0x7a]	21941	1			T6	6		T91	3		T47	85
valid_sources[0x7b]	21891	1			T23	2		T26	2		T6	30
valid_sources[0x7c]	22932	1			T23	1		T6	157		T91	2
valid_sources[0x7d]	22475	1			T23	2		T26	7		T6	33
valid_sources[0x7e]	22029	1			T26	1		T6	333		T12	2
valid_sources[0x7f]	21748	1			T26	3		T6	185		T12	6
valid_sources[0x80]	20820	1			T6	75		T37	3		T91	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1272485

1

T1

4

T2

7

T3

4

values[0x0]

all_enables

biggest_size

1890257

1

T1

2

T2

6

T3

17

values[0x1]

all_enables

biggest_size

1886747

1

T1

3

T2

1

T3

10