Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2720	1			T3	1		T26	2		T6	17
non_zero_bins[1]	1929	1			T3	1		T26	1		T6	5
zero	9429	1			T1	3		T2	3		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	537	1			T3	1		T6	2		T35	1
uni	3735	1			T1	1		T2	1		T3	2
gen	4445	1			T1	1		T2	1		T3	2
res	862	1			T26	1		T10	2		T6	4
ins	4499	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9291

1

T1

3

T2

2

T3

5

mubi_true

4787

1

T2

1

T3

2

T23

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

20

1

T111

1

T287

1

T162

1

pass

14058

1

T1

3

T2

3

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	130	1			T90	1		T96	1		T47	1
upd	non_zero_bins[0]	pass	mubi_true	106	1			T47	2		T57	1		T48	1
upd	non_zero_bins[1]	pass	mubi_false	102	1			T3	1		T6	1		T35	1
upd	non_zero_bins[1]	pass	mubi_true	94	1			T75	1		T298	1		T106	2
upd	zero	pass	mubi_false	54	1			T48	1		T75	1		T298	1
upd	zero	pass	mubi_true	51	1			T6	1		T47	2		T48	1
uni	zero	pass	mubi_false	2763	1			T1	1		T3	2		T5	1
uni	zero	pass	mubi_true	972	1			T2	1		T25	1		T6	6
gen	non_zero_bins[0]	pass	mubi_false	529	1			T6	1		T11	4		T34	1
gen	non_zero_bins[0]	pass	mubi_true	489	1			T3	1		T6	3		T90	1
gen	non_zero_bins[1]	pass	mubi_false	386	1			T26	1		T6	1		T47	5
gen	non_zero_bins[1]	pass	mubi_true	332	1			T47	2		T48	3		T13	7
gen	zero	fail	mubi_false	16	1			T111	1		T287	1		T299	1
gen	zero	pass	mubi_false	1932	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	761	1			T23	2		T5	1		T6	2
res	non_zero_bins[0]	pass	mubi_false	199	1			T26	1		T6	2		T11	3
res	non_zero_bins[0]	pass	mubi_true	196	1			T6	1		T48	1		T52	2
res	non_zero_bins[1]	pass	mubi_false	139	1			T6	1		T48	2		T21	1
res	non_zero_bins[1]	pass	mubi_true	122	1			T47	1		T48	1		T106	1
res	zero	fail	mubi_false	4	1			T162	1		T163	1		T300	1
res	zero	pass	mubi_false	101	1			T91	1		T48	1		T14	2
res	zero	pass	mubi_true	101	1			T10	2		T47	1		T48	1
ins	non_zero_bins[0]	pass	mubi_false	515	1			T6	8		T34	1		T36	1
ins	non_zero_bins[0]	pass	mubi_true	556	1			T26	1		T6	2		T35	1
ins	non_zero_bins[1]	pass	mubi_false	373	1			T6	1		T11	2		T12	1
ins	non_zero_bins[1]	pass	mubi_true	381	1			T6	1		T12	1		T47	3
ins	zero	pass	mubi_false	2048	1			T1	1		T2	1		T3	1
ins	zero	pass	mubi_true	626	1			T3	1		T23	1		T6	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded