Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T50,T16
1	1	Covered	T3,T23,T5

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23,T29,T30
1	0	Covered	T5,T16,T44

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T23,T29,T30
1	Covered	T5,T16,T44

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T23,T29,T30
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T23,T5,T29
1	Covered	T5,T16,T44

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T4,T5

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T11,T12
AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoCaptReseedCnt	141	Covered	T10,T11,T12
AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns	69	Covered	T10,T11,T12
AutoSendGenCmd	150	Covered	T10,T11,T12
AutoSendReseedCmd	162	Covered	T10,T11,T12
BootDone	98	Covered	T3,T5,T33
BootGenAckWait	90	Covered	T3,T5,T33
BootInsAckWait	80	Covered	T3,T5,T33
BootLoadGen	85	Covered	T3,T5,T33
BootLoadIns	65	Covered	T3,T23,T5
BootLoadUni	102	Covered	T3,T5,T34
BootPulse	94	Covered	T3,T5,T33
BootUniAckWait	107	Covered	T3,T5,T34
Error	188	Covered	T5,T16,T44
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T23,T29,T30
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T11,T12
AutoAckWait->Error	188	Covered	T7,T126,T127
AutoAckWait->Idle	211	Covered	T10,T11,T12
AutoAckWait->RejectCsrngEntropy	188	Covered	T89,T111,T95
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T11,T12
AutoCaptGenCnt->Error	188	Covered	T128,T129
AutoCaptGenCnt->Idle	211	Covered	T11,T130,T67
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T107,T101,T102
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T11,T12
AutoCaptReseedCnt->Error	188	Covered	T9,T131,T132
AutoCaptReseedCnt->Idle	211	Covered	T133,T134
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T135,T136,T137
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T11,T12
AutoDispatch->Error	188	Covered	T138,T139,T140
AutoDispatch->Idle	138	Covered	T13,T14,T52
AutoDispatch->RejectCsrngEntropy	188	Covered	T31,T22,T141
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait->Error	188	Covered	T142,T143,T144
AutoFirstAckWait->Idle	211	Covered	T21,T145,T146
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T147,T74,T148
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns->Error	188	Covered	T61,T149,T150
AutoLoadIns->Idle	211	Covered	T10,T29,T31
AutoLoadIns->RejectCsrngEntropy	188	Covered	T112,T151,T152
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T11,T12
AutoSendGenCmd->Error	188	Covered	T8,T153,T154
AutoSendGenCmd->Idle	211	Covered	T110,T155,T156
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T157,T158,T119
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T11,T12
AutoSendReseedCmd->Error	188	Covered	T159,T118
AutoSendReseedCmd->Idle	211	Covered	T12,T160,T161
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T162,T117,T163
BootDone->BootLoadUni	102	Covered	T3,T5,T34
BootDone->Error	188	Covered	T164,T165,T166
BootDone->Idle	211	Covered	T167,T78,T168
BootDone->RejectCsrngEntropy	188	Covered	T113,T169,T170
BootGenAckWait->BootPulse	94	Covered	T3,T5,T33
BootGenAckWait->Error	188	Covered	T171,T172,T173
BootGenAckWait->Idle	211	Covered	T50,T174,T88
BootGenAckWait->RejectCsrngEntropy	188	Covered	T175,T176,T177
BootInsAckWait->BootLoadGen	85	Covered	T3,T5,T33
BootInsAckWait->Error	188	Covered	T80,T71,T178
BootInsAckWait->Idle	211	Covered	T5,T16,T80
BootInsAckWait->RejectCsrngEntropy	188	Covered	T29,T108,T179
BootLoadGen->BootGenAckWait	90	Covered	T3,T5,T33
BootLoadGen->Error	188	Covered	T180
BootLoadGen->Idle	211	Covered	T181,T81,T87
BootLoadGen->RejectCsrngEntropy	188	Covered	T114,T182,T72
BootLoadIns->BootInsAckWait	80	Covered	T3,T5,T33
BootLoadIns->Error	188	Covered	T16,T183,T184
BootLoadIns->Idle	211	Covered	T185,T186,T187
BootLoadIns->RejectCsrngEntropy	188	Covered	T23,T188,T189
BootLoadUni->BootUniAckWait	107	Covered	T3,T5,T34
BootLoadUni->Error	188	Covered	T190,T191
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T30,T192,T193
BootPulse->BootDone	98	Covered	T3,T5,T33
BootPulse->Error	188	Not Covered
BootPulse->Idle	211	Covered	T194,T195,T196
BootPulse->RejectCsrngEntropy	188	Covered	T197,T198,T199
BootUniAckWait->Error	188	Covered	T5,T200,T201
BootUniAckWait->Idle	112	Covered	T3,T34,T49
BootUniAckWait->RejectCsrngEntropy	188	Covered	T32,T122,T120
Idle->AutoLoadIns	69	Covered	T10,T11,T12
Idle->BootLoadIns	65	Covered	T3,T23,T5
Idle->Error	188	Covered	T18,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T30,T22,T89
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T77,T60,T202
RejectCsrngEntropy->Idle	211	Covered	T23,T29,T30
SWPortMode->Error	188	Covered	T17,T99,T58
SWPortMode->Idle	211	Covered	T23,T4,T6
SWPortMode->RejectCsrngEntropy	188	Covered	T23,T29,T31

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T5
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T5
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T33
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T34
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T5,T33,T50
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T34
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T34,T49
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T34
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T13,T14,T52
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T12
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T11,T12
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T12
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T11,T12
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T29,T30
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T44
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T44,T78,T79

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T16,T44
1	0	1	-	Not Covered
1	0	0	-	Covered	T23,T29,T30
0	-	-	1	Covered	T23,T4,T5
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	198499533	124652	0	0
FpvSecCmErrorStEscalate_A	198499533	125436	0	0
u_state_regs_A	198460758	198305877	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	124652	0	0
T5	893	431	0	0
T6	229442	0	0	0
T7	0	462	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	572	0	0
T17	0	1161	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T44	0	148	0	0
T77	0	1105	0	0
T78	0	361	0	0
T79	0	300	0	0
T80	0	664	0	0
T98	0	1074	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	125436	0	0
T5	893	432	0	0
T6	229442	0	0	0
T7	0	463	0	0
T10	2419	0	0	0
T11	3650	0	0	0
T16	0	573	0	0
T17	0	1162	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T44	0	149	0	0
T77	0	1106	0	0
T78	0	362	0	0
T79	0	301	0	0
T80	0	665	0	0
T98	0	1075	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198460758	198305877	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1901	1743	0	0
T5	652	520	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0