Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T27,T28
1	0	1	Covered	T5,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	396412180	1029359	0	0
DepthKnown_A	396999066	396689304	0	0
RvalidKnown_A	396999066	396689304	0	0
WreadyKnown_A	396999066	396689304	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	396772212	1124176	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396412180	1029359	0	0
T6	458884	0	0	0
T10	4838	2138	0	0
T11	7300	6058	0	0
T12	4912	3104	0	0
T13	0	1601	0	0
T21	0	3974	0	0
T22	0	589	0	0
T29	5762	268	0	0
T30	0	286	0	0
T31	0	613	0	0
T32	0	221	0	0
T33	2124	0	0	0
T34	4996	0	0	0
T35	2466	0	0	0
T36	3354	0	0	0
T37	2116	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396999066	396689304	0	0
T1	2028	1844	0	0
T2	2820	2622	0	0
T3	3752	3564	0	0
T4	3906	3590	0	0
T5	1786	1522	0	0
T10	4838	4724	0	0
T23	3556	3398	0	0
T24	3760	3640	0	0
T25	1774	1630	0	0
T26	3920	3738	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396999066	396689304	0	0
T1	2028	1844	0	0
T2	2820	2622	0	0
T3	3752	3564	0	0
T4	3906	3590	0	0
T5	1786	1522	0	0
T10	4838	4724	0	0
T23	3556	3398	0	0
T24	3760	3640	0	0
T25	1774	1630	0	0
T26	3920	3738	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396999066	396689304	0	0
T1	2028	1844	0	0
T2	2820	2622	0	0
T3	3752	3564	0	0
T4	3906	3590	0	0
T5	1786	1522	0	0
T10	4838	4724	0	0
T23	3556	3398	0	0
T24	3760	3640	0	0
T25	1774	1630	0	0
T26	3920	3738	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	396772212	1124176	0	0
T5	1786	408	0	0
T6	458884	0	0	0
T10	4838	2138	0	0
T11	7300	6058	0	0
T12	0	3104	0	0
T16	0	220	0	0
T17	0	283	0	0
T21	0	3974	0	0
T24	3760	0	0	0
T25	1774	0	0	0
T26	3920	0	0	0
T29	0	268	0	0
T30	0	286	0	0
T31	0	613	0	0
T33	2124	0	0	0
T34	4996	0	0	0
T35	2466	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T39,T40,T41
1	0	1	Covered	T5,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	198206090	508587	0	0
DepthKnown_A	198499533	198344652	0	0
RvalidKnown_A	198499533	198344652	0	0
WreadyKnown_A	198499533	198344652	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	198386106	555568	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198206090	508587	0	0
T6	229442	0	0	0
T10	2419	992	0	0
T11	3650	3012	0	0
T12	2456	1508	0	0
T13	0	794	0	0
T21	0	1976	0	0
T22	0	295	0	0
T29	2881	77	0	0
T30	0	131	0	0
T31	0	295	0	0
T32	0	62	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	198386106	555568	0	0
T5	893	206	0	0
T6	229442	0	0	0
T10	2419	992	0	0
T11	3650	3012	0	0
T12	0	1508	0	0
T16	0	111	0	0
T17	0	143	0	0
T21	0	1976	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T29	0	77	0	0
T30	0	131	0	0
T31	0	295	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T27,T28
1	0	1	Covered	T5,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	198206090	520772	0	0
DepthKnown_A	198499533	198344652	0	0
RvalidKnown_A	198499533	198344652	0	0
WreadyKnown_A	198499533	198344652	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	198386106	568608	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198206090	520772	0	0
T6	229442	0	0	0
T10	2419	1146	0	0
T11	3650	3046	0	0
T12	2456	1596	0	0
T13	0	807	0	0
T21	0	1998	0	0
T22	0	294	0	0
T29	2881	191	0	0
T30	0	155	0	0
T31	0	318	0	0
T32	0	159	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0
T36	1677	0	0	0
T37	1058	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198499533	198344652	0	0
T1	1014	922	0	0
T2	1410	1311	0	0
T3	1876	1782	0	0
T4	1953	1795	0	0
T5	893	761	0	0
T10	2419	2362	0	0
T23	1778	1699	0	0
T24	1880	1820	0	0
T25	887	815	0	0
T26	1960	1869	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	198386106	568608	0	0
T5	893	202	0	0
T6	229442	0	0	0
T10	2419	1146	0	0
T11	3650	3046	0	0
T12	0	1596	0	0
T16	0	109	0	0
T17	0	140	0	0
T21	0	1998	0	0
T24	1880	0	0	0
T25	887	0	0	0
T26	1960	0	0	0
T29	0	191	0	0
T30	0	155	0	0
T31	0	318	0	0
T33	1062	0	0	0
T34	2498	0	0	0
T35	1233	0	0	0