Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.94	93.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	93.94	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.94	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	2	19	90.48

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	2	19	90.48	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	149	1			T1	1		T2	1		T22	1
auto_req_mode	139	1			T9	1		T13	1		T21	1
sw_mode	2597	1			T3	83		T4	42		T38	54

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

300

1

T22

1

T9

1

T13

1

single

100

1

T1

1

T2

1

T23

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1274	1			T1	1		T3	83		T22	1
auto[2]	63	1			T46	1		T45	1		T289	1
auto[3]	151	1			T60	32		T197	4		T290	11
auto[4]	28	1			T39	1		T47	1		T75	1
auto[5]	157	1			T4	42		T40	1		T78	1
auto[6]	21	1			T291	12		T292	4		T293	1
auto[7]	1191	1			T2	1		T61	1		T67	7

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	2	19	90.48	2

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[3]]	[auto_req_mode]	0	1	1
[auto[6]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	86	1			T1	1		T22	1		T23	1
auto[1]	auto_req_mode	85	1			T9	1		T13	1		T21	1
auto[1]	sw_mode	1103	1			T3	83		T38	54		T70	2
auto[2]	boot_req_mode	4	1			T46	1		T289	1		T294	1
auto[2]	auto_req_mode	4	1			T45	1		T295	1		T296	1
auto[2]	sw_mode	55	1			T297	1		T298	54		-	-
auto[3]	boot_req_mode	5	1			T283	1		T299	1		T300	1
auto[3]	sw_mode	146	1			T60	32		T197	4		T290	11
auto[4]	boot_req_mode	2	1			T301	1		T302	1		-	-
auto[4]	auto_req_mode	2	1			T303	1		T304	1		-	-
auto[4]	sw_mode	24	1			T39	1		T47	1		T75	1
auto[5]	boot_req_mode	6	1			T40	1		T82	1		T305	1
auto[5]	auto_req_mode	3	1			T78	1		T306	1		T307	1
auto[5]	sw_mode	148	1			T4	42		T308	10		T309	1
auto[6]	auto_req_mode	3	1			T310	1		T311	1		T312	1
auto[6]	sw_mode	18	1			T291	12		T292	4		T293	1
auto[7]	boot_req_mode	46	1			T2	1		T51	1		T313	1
auto[7]	auto_req_mode	42	1			T20	1		T10	1		T11	1
auto[7]	sw_mode	1103	1			T61	1		T67	7		T44	1