Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	640301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5187768

1

T1

23

T2

31

T3

143630

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1538091	1			T1	64		T2	288		T3	40892
values[0x0]	1982448	1			T1	12		T2	16		T3	54672
values[0x1]	2307530	1			T1	8		T2	13		T3	63899

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	315051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5513018

1

T1

40

T2

136

T3

152109

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22468	1			T3	601		T4	412		T38	538
valid_sources[0x01]	21987	1			T3	564		T4	426		T38	611
valid_sources[0x02]	22501	1			T1	1		T3	681		T4	241
valid_sources[0x03]	19692	1			T3	597		T4	308		T38	614
valid_sources[0x04]	23981	1			T3	649		T4	363		T27	1
valid_sources[0x05]	23038	1			T3	786		T4	372		T38	587
valid_sources[0x06]	22196	1			T3	639		T4	421		T5	1
valid_sources[0x07]	23531	1			T3	634		T4	463		T38	613
valid_sources[0x08]	22345	1			T3	555		T4	510		T8	3
valid_sources[0x09]	21544	1			T3	714		T4	352		T22	1
valid_sources[0x0a]	21517	1			T1	1		T3	518		T4	369
valid_sources[0x0b]	22729	1			T1	1		T3	604		T4	341
valid_sources[0x0c]	25084	1			T3	661		T4	476		T38	589
valid_sources[0x0d]	23375	1			T3	601		T4	378		T5	2
valid_sources[0x0e]	23736	1			T3	593		T4	332		T8	1
valid_sources[0x0f]	22781	1			T1	1		T3	729		T4	294
valid_sources[0x10]	24324	1			T3	671		T4	266		T38	628
valid_sources[0x11]	23223	1			T3	572		T4	473		T38	600
valid_sources[0x12]	24476	1			T3	492		T4	376		T38	628
valid_sources[0x13]	22798	1			T1	2		T3	651		T4	374
valid_sources[0x14]	20597	1			T3	551		T4	176		T27	1
valid_sources[0x15]	21833	1			T3	631		T4	301		T38	591
valid_sources[0x16]	22847	1			T1	2		T3	496		T4	343
valid_sources[0x17]	22572	1			T3	400		T4	316		T38	597
valid_sources[0x18]	23599	1			T3	508		T4	247		T38	567
valid_sources[0x19]	22125	1			T3	772		T4	353		T38	589
valid_sources[0x1a]	23028	1			T3	732		T4	383		T38	543
valid_sources[0x1b]	19801	1			T3	470		T4	335		T38	597
valid_sources[0x1c]	21160	1			T1	2		T3	500		T4	209
valid_sources[0x1d]	21188	1			T3	495		T4	254		T38	717
valid_sources[0x1e]	23923	1			T3	575		T4	381		T38	607
valid_sources[0x1f]	22468	1			T3	509		T4	328		T13	3
valid_sources[0x20]	23620	1			T3	735		T4	372		T38	605
valid_sources[0x21]	22568	1			T3	677		T4	475		T38	506
valid_sources[0x22]	22340	1			T3	563		T4	390		T38	614
valid_sources[0x23]	22335	1			T3	496		T4	412		T38	525
valid_sources[0x24]	21458	1			T3	636		T4	471		T38	507
valid_sources[0x25]	22993	1			T3	478		T4	265		T13	4
valid_sources[0x26]	24390	1			T3	542		T4	412		T38	598
valid_sources[0x27]	24266	1			T3	561		T4	422		T38	565
valid_sources[0x28]	21825	1			T3	704		T4	286		T38	600
valid_sources[0x29]	22324	1			T1	1		T3	678		T4	321
valid_sources[0x2a]	22699	1			T3	579		T4	431		T38	611
valid_sources[0x2b]	22348	1			T3	518		T4	306		T27	1
valid_sources[0x2c]	22078	1			T3	607		T4	297		T5	1
valid_sources[0x2d]	23155	1			T1	1		T3	653		T4	229
valid_sources[0x2e]	23726	1			T3	808		T4	201		T38	659
valid_sources[0x2f]	23973	1			T1	1		T3	688		T4	365
valid_sources[0x30]	21623	1			T3	539		T4	441		T38	620
valid_sources[0x31]	23145	1			T3	764		T4	374		T38	569
valid_sources[0x32]	22879	1			T1	1		T3	712		T4	373
valid_sources[0x33]	21327	1			T1	2		T3	613		T4	252
valid_sources[0x34]	21342	1			T3	609		T4	257		T38	521
valid_sources[0x35]	21022	1			T1	1		T3	495		T4	334
valid_sources[0x36]	20882	1			T3	792		T4	382		T38	601
valid_sources[0x37]	23985	1			T1	1		T3	697		T4	374
valid_sources[0x38]	23479	1			T1	1		T3	577		T4	383
valid_sources[0x39]	20848	1			T3	569		T4	348		T13	1
valid_sources[0x3a]	22667	1			T3	581		T4	441		T8	1
valid_sources[0x3b]	21903	1			T3	692		T4	384		T8	9
valid_sources[0x3c]	20522	1			T1	1		T3	600		T4	315
valid_sources[0x3d]	24380	1			T3	654		T4	427		T38	575
valid_sources[0x3e]	24360	1			T3	607		T4	347		T8	1
valid_sources[0x3f]	24639	1			T3	623		T4	451		T38	537
valid_sources[0x40]	22856	1			T3	546		T4	391		T38	630
valid_sources[0x41]	21584	1			T3	443		T4	513		T22	1
valid_sources[0x42]	23110	1			T3	633		T4	399		T38	617
valid_sources[0x43]	21921	1			T2	317		T3	654		T4	632
valid_sources[0x44]	22152	1			T3	504		T4	255		T38	539
valid_sources[0x45]	22279	1			T1	1		T3	563		T4	344
valid_sources[0x46]	24119	1			T3	550		T4	297		T8	2
valid_sources[0x47]	23527	1			T3	501		T4	358		T38	642
valid_sources[0x48]	23606	1			T3	598		T4	314		T27	1
valid_sources[0x49]	23828	1			T3	606		T4	380		T38	570
valid_sources[0x4a]	25877	1			T3	489		T4	357		T38	626
valid_sources[0x4b]	20939	1			T3	559		T4	456		T38	581
valid_sources[0x4c]	22041	1			T1	1		T3	608		T4	309
valid_sources[0x4d]	22889	1			T3	743		T4	305		T8	1
valid_sources[0x4e]	22519	1			T1	1		T3	637		T4	335
valid_sources[0x4f]	22426	1			T1	2		T3	705		T4	350
valid_sources[0x50]	23479	1			T3	658		T4	441		T13	1
valid_sources[0x51]	22302	1			T3	793		T4	289		T27	4
valid_sources[0x52]	24643	1			T3	578		T4	532		T8	1
valid_sources[0x53]	22043	1			T1	1		T3	646		T4	256
valid_sources[0x54]	23532	1			T3	664		T4	437		T13	4
valid_sources[0x55]	21208	1			T3	837		T4	333		T38	513
valid_sources[0x56]	22974	1			T3	725		T4	281		T38	656
valid_sources[0x57]	23018	1			T1	1		T3	699		T4	401
valid_sources[0x58]	25528	1			T1	1		T3	620		T4	261
valid_sources[0x59]	24911	1			T3	664		T4	315		T8	1
valid_sources[0x5a]	22013	1			T1	1		T3	646		T4	203
valid_sources[0x5b]	23086	1			T1	1		T3	630		T4	270
valid_sources[0x5c]	22597	1			T1	2		T3	686		T4	287
valid_sources[0x5d]	22475	1			T3	811		T4	290		T38	636
valid_sources[0x5e]	23294	1			T1	1		T3	656		T4	402
valid_sources[0x5f]	24692	1			T3	623		T4	351		T5	4
valid_sources[0x60]	24024	1			T1	1		T3	692		T4	399
valid_sources[0x61]	24439	1			T3	669		T4	559		T13	4
valid_sources[0x62]	22962	1			T3	424		T4	346		T38	699
valid_sources[0x63]	23567	1			T3	792		T4	297		T22	1
valid_sources[0x64]	20922	1			T3	753		T4	431		T38	523
valid_sources[0x65]	22233	1			T3	686		T4	461		T27	1
valid_sources[0x66]	22679	1			T3	656		T4	327		T27	1
valid_sources[0x67]	22254	1			T1	1		T3	538		T4	250
valid_sources[0x68]	22121	1			T3	576		T4	322		T5	1
valid_sources[0x69]	22679	1			T3	581		T4	423		T38	538
valid_sources[0x6a]	22686	1			T3	659		T4	414		T8	2
valid_sources[0x6b]	21558	1			T3	680		T4	293		T5	3
valid_sources[0x6c]	21486	1			T3	698		T4	272		T38	584
valid_sources[0x6d]	22674	1			T3	665		T4	339		T38	566
valid_sources[0x6e]	22749	1			T1	1		T3	582		T4	374
valid_sources[0x6f]	21432	1			T3	530		T4	350		T27	2
valid_sources[0x70]	22314	1			T3	661		T4	222		T38	616
valid_sources[0x71]	22998	1			T3	502		T4	386		T8	1
valid_sources[0x72]	21907	1			T3	579		T4	317		T13	4
valid_sources[0x73]	23583	1			T3	757		T4	465		T38	537
valid_sources[0x74]	22491	1			T3	546		T4	246		T5	3
valid_sources[0x75]	22422	1			T3	620		T4	389		T5	4
valid_sources[0x76]	22929	1			T1	2		T3	681		T4	503
valid_sources[0x77]	22907	1			T3	632		T4	183		T5	3
valid_sources[0x78]	23042	1			T3	799		T4	431		T38	499
valid_sources[0x79]	22506	1			T3	576		T4	262		T5	2
valid_sources[0x7a]	21442	1			T1	1		T3	622		T4	365
valid_sources[0x7b]	24216	1			T3	687		T4	486		T38	657
valid_sources[0x7c]	21263	1			T1	2		T3	630		T4	431
valid_sources[0x7d]	23911	1			T3	787		T4	316		T38	454
valid_sources[0x7e]	20994	1			T3	572		T4	267		T5	1
valid_sources[0x7f]	21355	1			T3	737		T4	451		T13	4
valid_sources[0x80]	24351	1			T1	1		T3	604		T4	383

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1307888

1

T1

7

T2

6

T3

36202

values[0x0]

all_enables

biggest_size

1941470

1

T1

10

T2

15

T3

53648

values[0x1]

all_enables

biggest_size

1938410

1

T1

6

T2

10

T3

53780