Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2515	1			T1	1		T2	2		T3	44
non_zero_bins[1]	1801	1			T2	1		T3	34		T4	25
zero	8677	1			T1	7		T2	4		T3	215

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	475	1			T2	1		T3	9		T4	5
uni	3391	1			T1	3		T2	2		T3	93
gen	4187	1			T1	2		T2	2		T3	83
res	809	1			T3	15		T4	9		T8	1
ins	4131	1			T1	3		T2	2		T3	93

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8460

1

T1

4

T2

6

T3

206

mubi_true

4533

1

T1

4

T2

1

T3

87

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

14

1

T101

1

T278

1

T279

1

pass

12979

1

T1

8

T2

7

T3

293

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	107	1			T3	2		T4	1		T38	2
upd	non_zero_bins[0]	pass	mubi_true	103	1			T3	2		T4	1		T38	1
upd	non_zero_bins[1]	pass	mubi_false	84	1			T2	1		T3	3		T4	2
upd	non_zero_bins[1]	pass	mubi_true	84	1			T3	1		T4	1		T69	5
upd	zero	pass	mubi_false	52	1			T38	3		T69	1		T226	1
upd	zero	pass	mubi_true	45	1			T3	1		T38	1		T228	2
uni	zero	pass	mubi_false	2485	1			T1	2		T2	2		T3	63
uni	zero	pass	mubi_true	906	1			T1	1		T3	30		T4	11
gen	non_zero_bins[0]	pass	mubi_false	461	1			T2	1		T3	4		T4	2
gen	non_zero_bins[0]	pass	mubi_true	482	1			T3	8		T4	5		T9	3
gen	non_zero_bins[1]	pass	mubi_false	352	1			T3	4		T4	6		T38	7
gen	non_zero_bins[1]	pass	mubi_true	387	1			T3	8		T4	4		T38	4
gen	zero	fail	mubi_false	13	1			T101	1		T278	1		T279	1
gen	zero	pass	mubi_false	1790	1			T1	1		T2	1		T3	53
gen	zero	pass	mubi_true	702	1			T1	1		T3	6		T8	2
res	non_zero_bins[0]	pass	mubi_false	205	1			T3	3		T4	1		T38	1
res	non_zero_bins[0]	pass	mubi_true	169	1			T3	3		T4	4		T9	1
res	non_zero_bins[1]	pass	mubi_false	104	1			T3	2		T4	2		T38	1
res	non_zero_bins[1]	pass	mubi_true	114	1			T3	2		T4	2		T13	1
res	zero	fail	mubi_false	1	1			T148	1		-	-		-	-
res	zero	pass	mubi_false	122	1			T3	3		T8	1		T9	5
res	zero	pass	mubi_true	94	1			T3	2		T38	2		T69	3
ins	non_zero_bins[0]	pass	mubi_false	490	1			T2	1		T3	10		T4	5
ins	non_zero_bins[0]	pass	mubi_true	498	1			T1	1		T3	12		T4	7
ins	non_zero_bins[1]	pass	mubi_false	320	1			T3	7		T4	3		T38	7
ins	non_zero_bins[1]	pass	mubi_true	356	1			T3	7		T4	5		T9	1
ins	zero	pass	mubi_false	1874	1			T1	1		T3	52		T4	25
ins	zero	pass	mubi_true	593	1			T1	1		T2	1		T3	5

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded