Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[10].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[11].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[12].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[13].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[14].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[15].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[16].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[17].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[18].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[19].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[6].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[7].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[8].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[9].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=20,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	20	20

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=4,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	4	4

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=2,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

SCORE	LINE
100.00	100.00

tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	3860	3860	0	0
OutputsKnown_A	825414344	824660744	0	0
gen_no_flops.OutputDelay_A	825414344	824660744	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3860	3860	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T13	4	4	0	0
T22	4	4	0	0
T23	4	4	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825414344	824660744	0	0
T1	7000	6752	0	0
T2	6488	6204	0	0
T3	2522652	2522608	0	0
T4	1731208	1731156	0	0
T5	8796	8320	0	0
T8	7796	7408	0	0
T9	13480	13188	0	0
T13	7448	7136	0	0
T22	4556	4204	0	0
T23	3968	3732	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825414344	824660744	0	0
T1	7000	6752	0	0
T2	6488	6204	0	0
T3	2522652	2522608	0	0
T4	1731208	1731156	0	0
T5	8796	8320	0	0
T8	7796	7408	0	0
T9	13480	13188	0	0
T13	7448	7136	0	0
T22	4556	4204	0	0
T23	3968	3732	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	20	20

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	206353586	206165186	0	0
gen_no_flops.OutputDelay_A	206353586	206165186	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	4	4

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	206353586	206165186	0	0
gen_no_flops.OutputDelay_A	206353586	206165186	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	206353586	206165186	0	0
gen_no_flops.OutputDelay_A	206353586	206165186	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	2	2

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	965	965	0	0
OutputsKnown_A	206353586	206165186	0	0
gen_no_flops.OutputDelay_A	206353586	206165186	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0