Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T8,T42
1	1	Covered	T1,T2,T22

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T9,T13
1	1	Covered	T5,T8,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T27,T28
1	0	Covered	T5,T14,T32

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T8,T27,T28
1	Covered	T5,T14,T32

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T8,T27,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T5,T8,T27
1	Covered	T5,T14,T32

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T8,T9,T13
AutoCaptGenCnt	143	Covered	T8,T9,T13
AutoCaptReseedCnt	141	Covered	T8,T9,T13
AutoDispatch	125	Covered	T8,T9,T13
AutoFirstAckWait	119	Covered	T8,T9,T13
AutoLoadIns	69	Covered	T5,T8,T9
AutoSendGenCmd	150	Covered	T8,T9,T13
AutoSendReseedCmd	162	Covered	T8,T9,T13
BootDone	98	Covered	T1,T2,T22
BootGenAckWait	90	Covered	T1,T2,T22
BootInsAckWait	80	Covered	T1,T2,T22
BootLoadGen	85	Covered	T1,T2,T22
BootLoadIns	65	Covered	T1,T2,T22
BootLoadUni	102	Covered	T1,T2,T27
BootPulse	94	Covered	T1,T2,T22
BootUniAckWait	107	Covered	T1,T2,T27
Error	188	Covered	T5,T14,T32
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T8,T27,T28
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T8,T9,T13
AutoAckWait->Error	188	Covered	T111,T112,T113
AutoAckWait->Idle	211	Covered	T9,T13,T21
AutoAckWait->RejectCsrngEntropy	188	Covered	T8,T27,T101
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T8,T9,T13
AutoCaptGenCnt->Error	188	Covered	T7,T114,T115
AutoCaptGenCnt->Idle	211	Covered	T76,T116,T117
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T81,T118,T119
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T8,T9,T13
AutoCaptReseedCnt->Error	188	Covered	T120,T121,T122
AutoCaptReseedCnt->Idle	211	Covered	T123,T124,T125
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T126,T127,T128
AutoDispatch->AutoCaptGenCnt	143	Covered	T8,T9,T13
AutoDispatch->AutoCaptReseedCnt	141	Covered	T8,T9,T13
AutoDispatch->Error	188	Covered	T6,T129,T130
AutoDispatch->Idle	138	Covered	T13,T66,T45
AutoDispatch->RejectCsrngEntropy	188	Covered	T131,T132,T133
AutoFirstAckWait->AutoDispatch	125	Covered	T8,T9,T13
AutoFirstAckWait->Error	188	Covered	T134
AutoFirstAckWait->Idle	211	Covered	T18,T86,T91
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T135,T136,T137
AutoLoadIns->AutoFirstAckWait	119	Covered	T8,T9,T13
AutoLoadIns->Error	188	Covered	T5,T54,T138
AutoLoadIns->Idle	211	Covered	T5,T28,T43
AutoLoadIns->RejectCsrngEntropy	188	Covered	T43,T74,T139
AutoSendGenCmd->AutoAckWait	156	Covered	T8,T9,T13
AutoSendGenCmd->Error	188	Covered	T104,T140,T106
AutoSendGenCmd->Idle	211	Covered	T19
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T41,T141,T142
AutoSendReseedCmd->AutoAckWait	168	Covered	T8,T9,T13
AutoSendReseedCmd->Error	188	Covered	T143
AutoSendReseedCmd->Idle	211	Covered	T21,T144,T145
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T146,T147,T148
BootDone->BootLoadUni	102	Covered	T1,T2,T27
BootDone->Error	188	Covered	T149,T57,T150
BootDone->Idle	211	Covered	T151,T152,T150
BootDone->RejectCsrngEntropy	188	Covered	T77,T153,T154
BootGenAckWait->BootPulse	94	Covered	T1,T2,T22
BootGenAckWait->Error	188	Covered	T56,T155,T156
BootGenAckWait->Idle	211	Covered	T42,T157,T158
BootGenAckWait->RejectCsrngEntropy	188	Covered	T107,T92,T159
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T22
BootInsAckWait->Error	188	Covered	T160,T161,T162
BootInsAckWait->Idle	211	Covered	T22,T163,T164
BootInsAckWait->RejectCsrngEntropy	188	Covered	T102,T165,T166
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T22
BootLoadGen->Error	188	Covered	T167
BootLoadGen->Idle	211	Covered	T168,T169,T170
BootLoadGen->RejectCsrngEntropy	188	Covered	T49,T171,T172
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T22
BootLoadIns->Error	188	Covered	T173,T174,T175
BootLoadIns->Idle	211	Covered	T176,T177,T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T179,T180,T181
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T27
BootLoadUni->Error	188	Covered	T182
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T183,T89,T184
BootPulse->BootDone	98	Covered	T1,T2,T22
BootPulse->Error	188	Covered	T163,T152,T185
BootPulse->Idle	211	Covered	T79,T186,T187
BootPulse->RejectCsrngEntropy	188	Covered	T188,T189,T190
BootUniAckWait->Error	188	Covered	T191
BootUniAckWait->Idle	112	Covered	T1,T2,T27
BootUniAckWait->RejectCsrngEntropy	188	Covered	T28,T88,T192
Idle->AutoLoadIns	69	Covered	T5,T8,T9
Idle->BootLoadIns	65	Covered	T1,T2,T22
Idle->Error	188	Covered	T14,T16,T17
Idle->RejectCsrngEntropy	188	Covered	T8,T27,T28
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T32,T193,T194
RejectCsrngEntropy->Idle	211	Covered	T8,T27,T28
SWPortMode->Error	188	Covered	T14,T15,T195
SWPortMode->Idle	211	Covered	T3,T4,T8
SWPortMode->RejectCsrngEntropy	188	Covered	T43,T49,T101

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T27
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T22,T23,T27
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T27
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T27
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T27
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T5,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T66,T45,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T97,T98

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T14,T32
1	0	1	-	Not Covered
1	0	0	-	Covered	T8,T27,T28
0	-	-	1	Covered	T22,T5,T8
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	206353586	156677	0	0
FpvSecCmErrorStEscalate_A	206353586	157852	0	0
u_state_regs_A	206311783	206123383	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	156677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	157852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206311783	206123383	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2019	1900	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0