Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T186,T187,T196
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T22,T85,T19
DataWait->Error	99	Covered	T5,T6,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T32,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1444475102	1108789	0	0
FpvSecCmErrorStEscalate_A	1444475102	1117014	0	0
u_state_regs_A	1444433299	1443114499	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444475102	1108789	0	0
T5	15393	7686	0	0
T6	0	5564	0	0
T7	0	1553	0	0
T8	13643	0	0	0
T9	23590	0	0	0
T13	13034	0	0	0
T14	0	104167	0	0
T15	0	7917	0	0
T23	6944	0	0	0
T27	14084	0	0	0
T32	0	4514	0	0
T38	4930093	0	0	0
T53	9793	0	0	0
T54	0	7854	0	0
T60	1652329	0	0	0
T61	11585	0	0	0
T138	0	7741	0	0
T163	0	7440	0	0
T195	0	2792	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444475102	1117014	0	0
T5	15393	7693	0	0
T6	0	5571	0	0
T7	0	1560	0	0
T8	13643	0	0	0
T9	23590	0	0	0
T13	13034	0	0	0
T14	0	105987	0	0
T15	0	7924	0	0
T23	6944	0	0	0
T27	14084	0	0	0
T32	0	4521	0	0
T38	4930093	0	0	0
T53	9793	0	0	0
T54	0	7861	0	0
T60	1652329	0	0	0
T61	11585	0	0	0
T138	0	7748	0	0
T163	0	7447	0	0
T195	0	2799	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1444433299	1443114499	0	0
T1	12250	11816	0	0
T2	11354	10857	0	0
T3	4414641	4414564	0	0
T4	3029614	3029523	0	0
T5	15213	14380	0	0
T8	13643	12964	0	0
T9	23590	23079	0	0
T13	13034	12488	0	0
T22	7973	7357	0	0
T23	6944	6531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T39,T40,T46
DataWait	75	Covered	T5,T39,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T39,T40,T46
DataWait->AckPls	80	Covered	T39,T40,T46
DataWait->Disabled	107	Covered	T201
DataWait->Error	99	Covered	T5,T6,T193
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T5,T39,T40
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T32,T7,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T39,T40,T46
Idle	-	1	0	-	Covered	T5,T39,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T39,T40,T46
DataWait	-	-	-	0	Covered	T5,T39,T40
AckPls	-	-	-	-	Covered	T39,T40,T46
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T40,T41
DataWait	75	Covered	T28,T40,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T40,T41
DataWait->AckPls	80	Covered	T28,T40,T41
DataWait->Disabled	107	Covered	T202
DataWait->Error	99	Covered	T203,T129,T204
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T28,T40,T41
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T28,T40,T41
Idle	-	1	0	-	Covered	T28,T40,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T28,T40,T41
DataWait	-	-	-	0	Covered	T28,T40,T41
AckPls	-	-	-	-	Covered	T28,T40,T41
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T13,T42
DataWait	75	Covered	T2,T13,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T13,T42
DataWait->AckPls	80	Covered	T2,T13,T42
DataWait->Disabled	107	Covered	T205,T206,T207
DataWait->Error	99	Covered	T7,T163,T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T13,T42
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T13,T42
Idle	-	1	0	-	Covered	T2,T13,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T13,T42
DataWait	-	-	-	0	Covered	T2,T13,T42
AckPls	-	-	-	-	Covered	T2,T13,T42
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T22,T43
DataWait	75	Covered	T2,T22,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T22,T43
DataWait->AckPls	80	Covered	T2,T22,T43
DataWait->Disabled	107	Covered	T22,T19,T164
DataWait->Error	99	Covered	T209,T210,T211
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T22,T43
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T22,T43
Idle	-	1	0	-	Covered	T2,T22,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T22,T43
DataWait	-	-	-	0	Covered	T2,T22,T43
AckPls	-	-	-	-	Covered	T2,T22,T43
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T186,T187
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T85,T157,T168
DataWait->Error	99	Covered	T54,T56,T57
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T16,T59
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T15,T55

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T32,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	156727	0	0
FpvSecCmErrorStEscalate_A	206353586	157902	0	0
u_state_regs_A	206311783	206123383	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	156727	0	0
T5	2199	1098	0	0
T6	0	752	0	0
T7	0	179	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	602	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1063	0	0
T163	0	1020	0	0
T195	0	356	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	157902	0	0
T5	2199	1099	0	0
T6	0	753	0	0
T7	0	180	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	603	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1064	0	0
T163	0	1021	0	0
T195	0	357	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206311783	206123383	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2019	1900	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T8,T9
DataWait	75	Covered	T2,T8,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T196
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T8,T9
DataWait->AckPls	80	Covered	T2,T8,T9
DataWait->Disabled	107	Covered	T76,T212,T213
DataWait->Error	99	Covered	T191,T214,T215
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T8,T9
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T8,T9
Idle	-	1	0	-	Covered	T2,T8,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T8,T9
DataWait	-	-	-	0	Covered	T2,T8,T9
AckPls	-	-	-	-	Covered	T2,T8,T9
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T5,T8

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T28,T44
DataWait	75	Covered	T2,T28,T44
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T14,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T216
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T28,T44
DataWait->AckPls	80	Covered	T2,T28,T44
DataWait->Disabled	107	Covered	T217,T116,T170
DataWait->Error	99	Covered	T218,T114,T219
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T14,T16,T17
EndPointClear->Disabled	107	Covered	T197,T198,T199
EndPointClear->Error	99	Covered	T14,T138,T200
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T28,T44
Idle->Disabled	107	Covered	T3,T4,T22
Idle->Error	99	Covered	T5,T32,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T28,T44
Idle	-	1	0	-	Covered	T2,T28,T44
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T28,T44
DataWait	-	-	-	0	Covered	T2,T44,T20
AckPls	-	-	-	-	Covered	T2,T28,T44
Error	-	-	-	-	Covered	T5,T14,T32
default	-	-	-	-	Covered	T14,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T14,T32
0	1	Covered	T22,T5,T8
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	206353586	158677	0	0
FpvSecCmErrorStEscalate_A	206353586	159852	0	0
u_state_regs_A	206353586	206165186	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	158677	0	0
T5	2199	1098	0	0
T6	0	802	0	0
T7	0	229	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	14881	0	0
T15	0	1131	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	652	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1122	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1113	0	0
T163	0	1070	0	0
T195	0	406	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	159852	0	0
T5	2199	1099	0	0
T6	0	803	0	0
T7	0	230	0	0
T8	1949	0	0	0
T9	3370	0	0	0
T13	1862	0	0	0
T14	0	15141	0	0
T15	0	1132	0	0
T23	992	0	0	0
T27	2012	0	0	0
T32	0	653	0	0
T38	704299	0	0	0
T53	1399	0	0	0
T54	0	1123	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T138	0	1114	0	0
T163	0	1071	0	0
T195	0	407	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0