Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T96
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T36,T37
1	0	1	Covered	T5,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411965918	626738	0	0
DepthKnown_A	412707172	412330372	0	0
RvalidKnown_A	412707172	412330372	0	0
WreadyKnown_A	412707172	412330372	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412339996	726799	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411965918	626738	0	0
T5	634	264	0	0
T8	3898	466	0	0
T9	6740	3783	0	0
T13	3724	2578	0	0
T21	0	3524	0	0
T23	1984	0	0	0
T27	4024	624	0	0
T28	0	257	0	0
T38	1408598	0	0	0
T41	0	465	0	0
T43	0	645	0	0
T53	2798	0	0	0
T60	472094	0	0	0
T61	3310	0	0	0
T74	0	356	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412707172	412330372	0	0
T1	3500	3376	0	0
T2	3244	3102	0	0
T3	1261326	1261304	0	0
T4	865604	865578	0	0
T5	4398	4160	0	0
T8	3898	3704	0	0
T9	6740	6594	0	0
T13	3724	3568	0	0
T22	2278	2102	0	0
T23	1984	1866	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412707172	412330372	0	0
T1	3500	3376	0	0
T2	3244	3102	0	0
T3	1261326	1261304	0	0
T4	865604	865578	0	0
T5	4398	4160	0	0
T8	3898	3704	0	0
T9	6740	6594	0	0
T13	3724	3568	0	0
T22	2278	2102	0	0
T23	1984	1866	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412707172	412330372	0	0
T1	3500	3376	0	0
T2	3244	3102	0	0
T3	1261326	1261304	0	0
T4	865604	865578	0	0
T5	4398	4160	0	0
T8	3898	3704	0	0
T9	6740	6594	0	0
T13	3724	3568	0	0
T22	2278	2102	0	0
T23	1984	1866	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412339996	726799	0	0
T5	4398	1683	0	0
T8	3898	466	0	0
T9	6740	3783	0	0
T13	3724	2578	0	0
T21	0	3524	0	0
T23	1984	0	0	0
T27	4024	624	0	0
T28	0	257	0	0
T38	1408598	0	0	0
T41	0	465	0	0
T43	0	645	0	0
T53	2798	0	0	0
T60	472094	0	0	0
T61	3310	0	0	0
T74	0	356	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T36,T37
1	0	1	Covered	T5,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	205982959	306350	0	0
DepthKnown_A	206353586	206165186	0	0
RvalidKnown_A	206353586	206165186	0	0
WreadyKnown_A	206353586	206165186	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206169998	355996	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205982959	306350	0	0
T5	317	141	0	0
T8	1949	239	0	0
T9	3370	1826	0	0
T13	1862	1286	0	0
T21	0	1703	0	0
T23	992	0	0	0
T27	2012	316	0	0
T28	0	106	0	0
T38	704299	0	0	0
T41	0	274	0	0
T43	0	264	0	0
T53	1399	0	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T74	0	183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206169998	355996	0	0
T5	2199	803	0	0
T8	1949	239	0	0
T9	3370	1826	0	0
T13	1862	1286	0	0
T21	0	1703	0	0
T23	992	0	0	0
T27	2012	316	0	0
T28	0	106	0	0
T38	704299	0	0	0
T41	0	274	0	0
T43	0	264	0	0
T53	1399	0	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T74	0	183	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T96
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30
1	0	1	Covered	T5,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T8,T9,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	205982959	320388	0	0
DepthKnown_A	206353586	206165186	0	0
RvalidKnown_A	206353586	206165186	0	0
WreadyKnown_A	206353586	206165186	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	206169998	370803	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205982959	320388	0	0
T5	317	123	0	0
T8	1949	227	0	0
T9	3370	1957	0	0
T13	1862	1292	0	0
T21	0	1821	0	0
T23	992	0	0	0
T27	2012	308	0	0
T28	0	151	0	0
T38	704299	0	0	0
T41	0	191	0	0
T43	0	381	0	0
T53	1399	0	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T74	0	173	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206353586	206165186	0	0
T1	1750	1688	0	0
T2	1622	1551	0	0
T3	630663	630652	0	0
T4	432802	432789	0	0
T5	2199	2080	0	0
T8	1949	1852	0	0
T9	3370	3297	0	0
T13	1862	1784	0	0
T22	1139	1051	0	0
T23	992	933	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	206169998	370803	0	0
T5	2199	880	0	0
T8	1949	227	0	0
T9	3370	1957	0	0
T13	1862	1292	0	0
T21	0	1821	0	0
T23	992	0	0	0
T27	2012	308	0	0
T28	0	151	0	0
T38	704299	0	0	0
T41	0	191	0	0
T43	0	381	0	0
T53	1399	0	0	0
T60	236047	0	0	0
T61	1655	0	0	0
T74	0	173	0	0