Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 34 0 34 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 9 0 9 100.00 100 1 1 0
cr_instantiate_intended 9 0 9 100.00 100 1 1 0
cr_reseed_intended 8 0 8 100.00 100 1 1 0
cr_update_intended 2 0 2 100.00 100 1 1 0
cr_uninstantiate_intended 1 0 1 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 4110 1 T1 1 T2 1 T3 2
auto[RES] 1136 1 T2 1 T3 1 T21 1
auto[GEN] 4231 1 T1 1 T2 4 T3 2
auto[UPD] 496 1 T31 6 T247 1 T100 1
auto[UNI] 3325 1 T3 1 T21 1 T13 1


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 4437 1 T2 2 T3 3 T21 3
no_cmd_data 8869 1 T1 2 T2 4 T3 3


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 11460 1 T1 2 T2 3 T3 4
reseed_cmd 619 1 T2 1 T3 1 T4 1
generate_cmd 578 1 T2 1 T3 1 T4 1
boot_gen_cmd 366 1 T2 1 T20 1 T21 1
boot_ins_cmd 283 1 T20 1 T21 1 T4 2


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 4533 1 T2 3 T3 2 T20 2
false 8773 1 T1 2 T2 3 T3 4


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1419 1 T2 1 T3 3 T20 1
one 2499 1 T1 1 T2 4 T20 1


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 10456 1 T1 2 T3 2 T21 4
boot_mode 721 1 T2 1 T20 2 T21 2
auto_mode 2129 1 T2 5 T3 4 T13 4


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 180 1 T3 1 T21 1 T13 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 143 1 T9 1 T67 1 T70 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 56 1 T52 1 T100 1 T350 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 154 1 T2 1 T13 1 T19 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 47 1 T35 1 T99 1 T12 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 65 1 T21 1 T100 1 T304 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 25 1 T3 1 T10 1 T67 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1323 1 T1 1 T5 1 T31 29
auto[GEN] no_cmd_data one auto_mode generate_cmd 197 1 T9 1 T6 1 T87 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 793 1 T31 4 T50 1 T52 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 92 1 T10 1 T64 2 T65 2
auto[INS] some_cmd_data false sw_mode sw_cmd_req 777 1 T21 1 T31 14 T35 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 90 1 T3 1 T13 1 T19 2
auto[INS] no_cmd_data true sw_mode sw_cmd_req 186 1 T31 1 T43 1 T32 5
auto[INS] no_cmd_data true auto_mode sw_cmd_req 218 1 T2 1 T3 1 T13 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1508 1 T1 1 T5 1 T14 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 144 1 T21 1 T4 2 T51 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 163 1 T9 1 T6 1 T87 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 191 1 T31 3 T50 1 T99 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 153 1 T13 1 T10 1 T6 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 207 1 T21 1 T31 5 T52 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 143 1 T2 1 T3 1 T9 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 55 1 T304 1 T223 1 T224 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 37 1 T19 1 T293 1 T85 2
auto[RES] no_cmd_data false sw_mode sw_cmd_req 45 1 T31 1 T96 1 T97 1
auto[RES] no_cmd_data false auto_mode reseed_cmd 227 1 T9 1 T6 2 T64 2


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 389 1 T31 5 T247 1 T100 1
auto[UPD] no_cmd_data sw_mode sw_cmd_req 89 1 T31 1 T32 3 T33 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 1 0 1 100.00
Automatically Generated Cross Bins 1 0 1 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3301 1 T3 1 T21 1 T13 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 563 1 T2 1 T3 2 T13 2
auto[RES] auto_mode sw_cmd_req 19 1 T79 1 T351 1 T352 1
auto[GEN] auto_mode sw_cmd_req 418 1 T2 2 T9 2 T25 2
auto[UPD] auto_mode sw_cmd_req 18 1 T11 1 T77 1 T78 1
auto[UNI] auto_mode sw_cmd_req 24 1 T10 1 T318 1 T82 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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