Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	644649	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5286966

1

T1

6

T2

58

T3

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1562230	1			T1	16		T2	27		T3	89
values[0x0]	2022501	1			T1	4		T2	35		T3	27
values[0x1]	2346884	1			T1	8		T2	21		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	317534	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5614081

1

T1

6

T2

61

T3

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22749	1			T31	259		T42	2		T7	1
valid_sources[0x01]	23245	1			T31	250		T52	1		T7	1
valid_sources[0x02]	21189	1			T10	2		T19	1		T31	220
valid_sources[0x03]	21249	1			T31	165		T306	2		T103	1
valid_sources[0x04]	20472	1			T1	1		T21	1		T10	1
valid_sources[0x05]	22533	1			T31	198		T51	3		T72	2
valid_sources[0x06]	23059	1			T5	1		T19	1		T31	156
valid_sources[0x07]	22163	1			T31	231		T6	2		T87	1
valid_sources[0x08]	22554	1			T19	1		T31	248		T6	2
valid_sources[0x09]	24913	1			T19	1		T31	183		T7	1
valid_sources[0x0a]	24497	1			T19	3		T31	210		T9	3
valid_sources[0x0b]	23758	1			T31	188		T87	3		T35	1
valid_sources[0x0c]	24072	1			T10	1		T19	4		T31	176
valid_sources[0x0d]	23517	1			T2	1		T20	1		T31	168
valid_sources[0x0e]	23882	1			T10	1		T31	229		T67	1
valid_sources[0x0f]	23873	1			T21	1		T10	1		T31	185
valid_sources[0x10]	22978	1			T10	1		T31	182		T103	2
valid_sources[0x11]	21636	1			T5	1		T31	134		T100	2
valid_sources[0x12]	23936	1			T19	1		T31	215		T72	1
valid_sources[0x13]	22339	1			T21	3		T10	1		T19	1
valid_sources[0x14]	22134	1			T19	1		T31	152		T7	1
valid_sources[0x15]	23790	1			T2	1		T20	2		T10	1
valid_sources[0x16]	22702	1			T2	1		T19	3		T31	135
valid_sources[0x17]	23280	1			T31	121		T247	6		T67	1
valid_sources[0x18]	22797	1			T13	4		T31	179		T52	1
valid_sources[0x19]	23778	1			T1	1		T5	1		T19	2
valid_sources[0x1a]	24329	1			T4	17		T13	1		T31	142
valid_sources[0x1b]	25020	1			T13	1		T31	193		T52	3
valid_sources[0x1c]	23094	1			T31	200		T42	1		T35	1
valid_sources[0x1d]	23138	1			T2	2		T5	1		T10	1
valid_sources[0x1e]	23509	1			T14	1		T10	3		T19	1
valid_sources[0x1f]	23048	1			T5	1		T19	1		T31	154
valid_sources[0x20]	22246	1			T10	1		T31	134		T105	1
valid_sources[0x21]	24832	1			T2	1		T31	183		T67	1
valid_sources[0x22]	23815	1			T1	1		T21	2		T31	173
valid_sources[0x23]	22691	1			T21	1		T31	219		T50	3
valid_sources[0x24]	25258	1			T10	1		T31	249		T25	10
valid_sources[0x25]	23900	1			T13	6		T31	209		T25	1
valid_sources[0x26]	23054	1			T31	168		T52	2		T41	1
valid_sources[0x27]	24932	1			T21	1		T31	149		T52	3
valid_sources[0x28]	24191	1			T13	1		T31	198		T7	1
valid_sources[0x29]	22985	1			T10	2		T19	3		T31	127
valid_sources[0x2a]	23339	1			T10	2		T19	1		T31	189
valid_sources[0x2b]	24095	1			T19	1		T31	280		T65	2
valid_sources[0x2c]	22439	1			T19	3		T31	181		T67	1
valid_sources[0x2d]	23128	1			T1	1		T10	1		T19	4
valid_sources[0x2e]	22668	1			T10	1		T31	198		T52	1
valid_sources[0x2f]	22778	1			T2	1		T31	191		T229	35
valid_sources[0x30]	22292	1			T2	1		T5	1		T31	170
valid_sources[0x31]	22728	1			T2	1		T13	6		T31	154
valid_sources[0x32]	24560	1			T5	1		T13	2		T19	1
valid_sources[0x33]	24560	1			T19	1		T31	141		T52	1
valid_sources[0x34]	24242	1			T21	2		T5	1		T19	1
valid_sources[0x35]	23677	1			T5	1		T31	155		T52	1
valid_sources[0x36]	23143	1			T21	1		T10	2		T19	1
valid_sources[0x37]	23855	1			T21	1		T31	165		T87	1
valid_sources[0x38]	22379	1			T5	2		T31	153		T87	1
valid_sources[0x39]	24195	1			T1	1		T13	3		T31	183
valid_sources[0x3a]	23100	1			T10	3		T31	232		T50	1
valid_sources[0x3b]	21662	1			T5	1		T31	216		T65	4
valid_sources[0x3c]	24461	1			T21	1		T31	199		T100	1
valid_sources[0x3d]	22953	1			T10	1		T31	170		T71	1
valid_sources[0x3e]	23274	1			T31	114		T65	1		T105	1
valid_sources[0x3f]	21723	1			T31	229		T65	1		T36	1
valid_sources[0x40]	23824	1			T21	2		T31	190		T9	2
valid_sources[0x41]	22722	1			T1	1		T5	1		T31	184
valid_sources[0x42]	23797	1			T31	145		T9	4		T87	1
valid_sources[0x43]	23175	1			T13	2		T31	195		T87	1
valid_sources[0x44]	22641	1			T14	1		T31	199		T67	2
valid_sources[0x45]	23192	1			T21	1		T14	1		T13	1
valid_sources[0x46]	24284	1			T5	1		T10	2		T31	153
valid_sources[0x47]	22241	1			T13	20		T31	143		T7	3
valid_sources[0x48]	23137	1			T21	1		T31	177		T87	3
valid_sources[0x49]	23672	1			T31	143		T52	1		T35	1
valid_sources[0x4a]	24293	1			T21	1		T19	2		T31	155
valid_sources[0x4b]	23366	1			T31	266		T52	1		T72	8
valid_sources[0x4c]	22975	1			T31	235		T72	1		T65	3
valid_sources[0x4d]	24865	1			T2	1		T21	1		T10	2
valid_sources[0x4e]	22401	1			T19	3		T31	217		T42	2
valid_sources[0x4f]	23231	1			T19	1		T31	173		T72	2
valid_sources[0x50]	22050	1			T5	2		T19	1		T31	164
valid_sources[0x51]	24062	1			T10	1		T19	2		T31	244
valid_sources[0x52]	22852	1			T1	1		T21	1		T5	1
valid_sources[0x53]	22350	1			T19	2		T31	174		T25	1
valid_sources[0x54]	21769	1			T19	1		T31	215		T65	4
valid_sources[0x55]	23398	1			T10	1		T19	1		T31	123
valid_sources[0x56]	23576	1			T21	2		T5	2		T19	1
valid_sources[0x57]	23766	1			T10	1		T19	3		T31	161
valid_sources[0x58]	23429	1			T31	143		T87	1		T105	1
valid_sources[0x59]	22416	1			T13	8		T10	1		T31	180
valid_sources[0x5a]	24821	1			T31	202		T9	2		T104	1
valid_sources[0x5b]	25258	1			T2	1		T31	144		T43	307
valid_sources[0x5c]	22760	1			T21	1		T10	1		T31	156
valid_sources[0x5d]	21939	1			T21	1		T5	1		T13	2
valid_sources[0x5e]	22513	1			T2	1		T21	1		T31	148
valid_sources[0x5f]	23173	1			T31	223		T87	1		T41	1
valid_sources[0x60]	22433	1			T31	156		T25	4		T247	7
valid_sources[0x61]	22877	1			T21	1		T10	1		T31	174
valid_sources[0x62]	23664	1			T19	1		T31	224		T100	1
valid_sources[0x63]	22627	1			T10	1		T31	133		T6	1
valid_sources[0x64]	23604	1			T2	2		T21	2		T10	1
valid_sources[0x65]	23704	1			T5	1		T10	3		T31	143
valid_sources[0x66]	22313	1			T31	185		T52	1		T87	4
valid_sources[0x67]	21553	1			T31	109		T35	2		T67	1
valid_sources[0x68]	25286	1			T1	1		T19	2		T31	325
valid_sources[0x69]	23092	1			T31	221		T67	1		T98	2
valid_sources[0x6a]	23238	1			T10	1		T19	1		T31	180
valid_sources[0x6b]	24638	1			T10	1		T31	212		T50	3
valid_sources[0x6c]	25023	1			T10	4		T31	197		T35	1
valid_sources[0x6d]	21624	1			T31	226		T87	2		T306	9
valid_sources[0x6e]	24133	1			T31	199		T64	123		T65	2
valid_sources[0x6f]	22389	1			T21	1		T10	1		T19	1
valid_sources[0x70]	23427	1			T2	1		T14	1		T10	1
valid_sources[0x71]	25091	1			T14	1		T13	5		T10	1
valid_sources[0x72]	22718	1			T10	1		T31	212		T67	1
valid_sources[0x73]	22881	1			T1	1		T10	1		T31	234
valid_sources[0x74]	22139	1			T1	1		T21	1		T15	4
valid_sources[0x75]	22420	1			T31	253		T50	2		T9	1
valid_sources[0x76]	23104	1			T19	2		T31	144		T52	1
valid_sources[0x77]	23653	1			T21	1		T19	2		T31	234
valid_sources[0x78]	22579	1			T10	2		T19	1		T31	198
valid_sources[0x79]	23783	1			T19	2		T31	159		T50	3
valid_sources[0x7a]	24118	1			T19	1		T31	254		T9	3
valid_sources[0x7b]	24077	1			T21	2		T10	1		T19	1
valid_sources[0x7c]	23548	1			T31	190		T72	4		T105	1
valid_sources[0x7d]	21449	1			T14	1		T10	1		T31	142
valid_sources[0x7e]	22458	1			T1	1		T10	1		T19	1
valid_sources[0x7f]	22484	1			T21	1		T31	179		T50	1
valid_sources[0x80]	22392	1			T2	1		T19	3		T31	151

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1330218

1

T1

4

T2

16

T3

2

values[0x0]

all_enables

biggest_size

1980631

1

T1

1

T2

28

T3

23

values[0x1]

all_enables

biggest_size

1976117

1

T1

1

T2

14

T3

22