Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2569	1			T3	2		T21	2		T13	26
non_zero_bins[1]	1878	1			T3	2		T21	1		T13	3
zero	8714	1			T1	2		T2	5		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	478	1			T31	6		T247	1		T100	1
uni	3430	1			T3	1		T21	2		T13	1
gen	4216	1			T1	1		T2	3		T3	4
res	871	1			T3	2		T21	1		T13	2
ins	4166	1			T1	1		T2	2		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8592

1

T1

2

T2

2

T3

7

mubi_true

4569

1

T2

3

T3

1

T20

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

28

1

T103

1

T88

1

T291

1

pass

13133

1

T1

2

T2

5

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	122	1			T31	1		T247	1		T43	2
upd	non_zero_bins[0]	pass	mubi_true	107	1			T31	4		T100	1		T32	1
upd	non_zero_bins[1]	pass	mubi_false	79	1			T32	1		T194	1		T97	1
upd	non_zero_bins[1]	pass	mubi_true	81	1			T33	1		T302	1		T101	1
upd	zero	pass	mubi_false	48	1			T32	2		T33	1		T97	2
upd	zero	pass	mubi_true	41	1			T31	1		T32	1		T39	1
uni	zero	pass	mubi_false	2541	1			T3	1		T21	2		T13	1
uni	zero	pass	mubi_true	889	1			T31	14		T72	1		T35	1
gen	non_zero_bins[0]	pass	mubi_false	471	1			T13	26		T31	2		T43	1
gen	non_zero_bins[0]	pass	mubi_true	500	1			T3	1		T31	4		T50	1
gen	non_zero_bins[1]	pass	mubi_false	351	1			T10	1		T19	1		T31	5
gen	non_zero_bins[1]	pass	mubi_true	356	1			T21	1		T19	9		T31	3
gen	zero	fail	mubi_false	25	1			T103	1		T88	1		T291	1
gen	zero	pass	mubi_false	1792	1			T1	1		T2	1		T3	3
gen	zero	pass	mubi_true	721	1			T2	2		T20	1		T21	1
res	non_zero_bins[0]	pass	mubi_false	193	1			T21	1		T31	3		T52	1
res	non_zero_bins[0]	pass	mubi_true	189	1			T31	1		T50	1		T67	2
res	non_zero_bins[1]	pass	mubi_false	131	1			T3	2		T31	2		T70	1
res	non_zero_bins[1]	pass	mubi_true	147	1			T13	2		T10	2		T31	2
res	zero	fail	mubi_false	3	1			T149	1		T150	1		T303	1
res	zero	pass	mubi_false	105	1			T31	1		T64	4		T87	1
res	zero	pass	mubi_true	103	1			T19	2		T304	1		T293	2
ins	non_zero_bins[0]	pass	mubi_false	488	1			T3	1		T21	1		T31	9
ins	non_zero_bins[0]	pass	mubi_true	499	1			T10	1		T31	2		T50	1
ins	non_zero_bins[1]	pass	mubi_false	368	1			T13	1		T19	1		T31	5
ins	non_zero_bins[1]	pass	mubi_true	365	1			T31	2		T64	2		T100	1
ins	zero	pass	mubi_false	1875	1			T1	1		T2	1		T21	1
ins	zero	pass	mubi_true	571	1			T2	1		T20	2		T31	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded