Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T28,T86
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T29,T30
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T13,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415108360	2360072	0	0
DepthKnown_A	415765132	415409536	0	0
RvalidKnown_A	415765132	415409536	0	0
WreadyKnown_A	415765132	415409536	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	415456228	2443563	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415108360	2360072	0	0
T2	3652	303	0	0
T3	8858	3424	0	0
T4	280	0	0	0
T5	350	0	0	0
T6	0	93	0	0
T9	0	1184	0	0
T10	8288	3387	0	0
T13	7910	4049	0	0
T14	146	0	0	0
T15	172	0	0	0
T19	0	3943	0	0
T20	2166	0	0	0
T21	4442	0	0	0
T42	0	633	0	0
T64	0	2617	0	0
T87	0	1136	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415765132	415409536	0	0
T1	2742	2386	0	0
T2	3652	3480	0	0
T3	8858	8746	0	0
T4	1420	1036	0	0
T5	1344	1060	0	0
T13	7910	7810	0	0
T14	1158	858	0	0
T15	1546	1282	0	0
T20	2166	1974	0	0
T21	4442	4336	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415765132	415409536	0	0
T1	2742	2386	0	0
T2	3652	3480	0	0
T3	8858	8746	0	0
T4	1420	1036	0	0
T5	1344	1060	0	0
T13	7910	7810	0	0
T14	1158	858	0	0
T15	1546	1282	0	0
T20	2166	1974	0	0
T21	4442	4336	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415765132	415409536	0	0
T1	2742	2386	0	0
T2	3652	3480	0	0
T3	8858	8746	0	0
T4	1420	1036	0	0
T5	1344	1060	0	0
T13	7910	7810	0	0
T14	1158	858	0	0
T15	1546	1282	0	0
T20	2166	1974	0	0
T21	4442	4336	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	415456228	2443563	0	0
T1	1371	36	0	0
T2	3652	303	0	0
T3	8858	3424	0	0
T4	1420	354	0	0
T5	1344	0	0	0
T6	0	452	0	0
T9	0	1184	0	0
T10	4144	3387	0	0
T13	7910	4049	0	0
T14	1158	362	0	0
T15	1546	293	0	0
T19	0	3943	0	0
T20	2166	0	0	0
T21	4442	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T66,T88
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T89,T90
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T3,T13,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	207554180	1174901	0	0
DepthKnown_A	207882566	207704768	0	0
RvalidKnown_A	207882566	207704768	0	0
WreadyKnown_A	207882566	207704768	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207728114	1216608	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207554180	1174901	0	0
T2	1826	147	0	0
T3	4429	1715	0	0
T4	140	0	0	0
T5	175	0	0	0
T6	0	39	0	0
T9	0	652	0	0
T10	4144	1690	0	0
T13	3955	2015	0	0
T14	73	0	0	0
T15	86	0	0	0
T19	0	1927	0	0
T20	1083	0	0	0
T21	2221	0	0	0
T42	0	325	0	0
T64	0	1281	0	0
T87	0	551	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207728114	1216608	0	0
T2	1826	147	0	0
T3	4429	1715	0	0
T4	710	179	0	0
T5	672	0	0	0
T6	0	452	0	0
T9	0	652	0	0
T10	4144	1690	0	0
T13	3955	2015	0	0
T14	579	187	0	0
T15	773	149	0	0
T19	0	1927	0	0
T20	1083	0	0	0
T21	2221	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T86,T91
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T30,T92
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T13,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	207554180	1185171	0	0
DepthKnown_A	207882566	207704768	0	0
RvalidKnown_A	207882566	207704768	0	0
WreadyKnown_A	207882566	207704768	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207728114	1226955	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207554180	1185171	0	0
T2	1826	156	0	0
T3	4429	1709	0	0
T4	140	0	0	0
T5	175	0	0	0
T6	0	54	0	0
T9	0	532	0	0
T10	4144	1697	0	0
T13	3955	2034	0	0
T14	73	0	0	0
T15	86	0	0	0
T19	0	2016	0	0
T20	1083	0	0	0
T21	2221	0	0	0
T42	0	308	0	0
T64	0	1336	0	0
T87	0	585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207882566	207704768	0	0
T1	1371	1193	0	0
T2	1826	1740	0	0
T3	4429	4373	0	0
T4	710	518	0	0
T5	672	530	0	0
T13	3955	3905	0	0
T14	579	429	0	0
T15	773	641	0	0
T20	1083	987	0	0
T21	2221	2168	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207728114	1226955	0	0
T1	1371	36	0	0
T2	1826	156	0	0
T3	4429	1709	0	0
T4	710	175	0	0
T5	672	0	0	0
T9	0	532	0	0
T10	0	1697	0	0
T13	3955	2034	0	0
T14	579	175	0	0
T15	773	144	0	0
T19	0	2016	0	0
T20	1083	0	0	0
T21	2221	0	0	0