Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	137	1			T18	1		T46	1		T40	1
auto_req_mode	143	1			T3	1		T7	1		T8	1
sw_mode	2770	1			T20	1		T53	5		T54	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

284

1

T18

1

T8

1

T15

1

single

116

1

T3

1

T7

1

T20

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1299	1			T3	1		T18	1		T20	1
auto[2]	123	1			T73	1		T34	32		T322	1
auto[3]	129	1			T85	1		T45	1		T323	1
auto[4]	92	1			T324	1		T325	1		T326	1
auto[5]	120	1			T74	1		T327	1		T328	1
auto[6]	129	1			T7	1		T47	1		T75	1
auto[7]	1158	1			T54	1		T37	1		T17	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	88	1			T18	1		T46	1		T40	1
auto[1]	auto_req_mode	80	1			T3	1		T8	1		T15	1
auto[1]	sw_mode	1131	1			T20	1		T53	5		T249	1
auto[2]	boot_req_mode	4	1			T329	1		T260	1		T330	1
auto[2]	auto_req_mode	3	1			T322	1		T331	1		T332	1
auto[2]	sw_mode	116	1			T73	1		T34	32		T333	24
auto[3]	boot_req_mode	3	1			T76	1		T334	1		T335	1
auto[3]	auto_req_mode	4	1			T85	1		T323	1		T336	1
auto[3]	sw_mode	122	1			T45	1		T337	1		T338	10
auto[4]	boot_req_mode	1	1			T325	1		-	-		-	-
auto[4]	auto_req_mode	2	1			T324	1		T326	1		-	-
auto[4]	sw_mode	89	1			T234	27		T339	2		T340	5
auto[5]	boot_req_mode	2	1			T341	1		T342	1		-	-
auto[5]	auto_req_mode	9	1			T74	1		T328	1		T343	1
auto[5]	sw_mode	109	1			T327	1		T344	1		T345	62
auto[6]	boot_req_mode	3	1			T346	1		T347	1		T348	1
auto[6]	auto_req_mode	7	1			T7	1		T349	1		T350	1
auto[6]	sw_mode	119	1			T47	1		T75	1		T232	82
auto[7]	boot_req_mode	36	1			T41	1		T48	1		T351	1
auto[7]	auto_req_mode	38	1			T17	1		T44	1		T10	1
auto[7]	sw_mode	1084	1			T54	1		T37	1		T39	1