Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	628389	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5006316

1

T1

11

T2

14

T3

69

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1497262	1			T1	4		T2	4		T3	29
values[0x0]	1914555	1			T1	9		T2	8		T3	36
values[0x1]	2222888	1			T1	5		T2	5		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5321011

1

T1

14

T2

14

T3

81

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21282	1			T22	1		T37	1		T17	1
valid_sources[0x01]	20472	1			T17	1		T72	1		T9	2
valid_sources[0x02]	20818	1			T21	2		T53	1		T5	1
valid_sources[0x03]	22043	1			T53	9		T5	1		T15	1
valid_sources[0x04]	23221	1			T61	1		T15	3		T69	2
valid_sources[0x05]	21666	1			T15	1		T17	1		T85	1
valid_sources[0x06]	21174	1			T21	2		T38	1		T73	1
valid_sources[0x07]	23829	1			T19	1		T53	4		T37	1
valid_sources[0x08]	23457	1			T4	1		T53	1		T61	2
valid_sources[0x09]	22623	1			T20	1		T22	3		T4	2
valid_sources[0x0a]	23204	1			T19	2		T20	4		T21	1
valid_sources[0x0b]	22629	1			T17	1		T72	2		T55	1
valid_sources[0x0c]	23321	1			T21	2		T4	1		T54	10
valid_sources[0x0d]	22195	1			T5	1		T37	1		T72	1
valid_sources[0x0e]	22369	1			T19	1		T38	34		T15	1
valid_sources[0x0f]	19936	1			T20	1		T53	2		T11	27
valid_sources[0x10]	22173	1			T53	2		T38	1		T5	1
valid_sources[0x11]	22156	1			T61	1		T69	1		T17	1
valid_sources[0x12]	21671	1			T20	1		T53	3		T17	3
valid_sources[0x13]	21634	1			T22	4		T53	3		T15	2
valid_sources[0x14]	22163	1			T18	6		T53	5		T37	1
valid_sources[0x15]	20742	1			T50	1		T73	1		T82	2
valid_sources[0x16]	21250	1			T19	2		T54	2		T113	1
valid_sources[0x17]	21066	1			T33	43		T53	3		T11	28
valid_sources[0x18]	23326	1			T20	3		T15	1		T69	2
valid_sources[0x19]	23803	1			T4	1		T53	3		T37	1
valid_sources[0x1a]	20830	1			T21	4		T12	1		T5	2
valid_sources[0x1b]	22509	1			T37	2		T17	2		T73	1
valid_sources[0x1c]	21831	1			T53	12		T38	2		T9	1
valid_sources[0x1d]	22783	1			T19	2		T11	1		T15	2
valid_sources[0x1e]	22335	1			T11	44		T38	1		T15	3
valid_sources[0x1f]	22256	1			T20	1		T21	1		T17	2
valid_sources[0x20]	21838	1			T1	17		T15	1		T17	2
valid_sources[0x21]	21877	1			T19	4		T53	1		T5	1
valid_sources[0x22]	22561	1			T22	2		T53	4		T5	1
valid_sources[0x23]	20692	1			T20	2		T21	2		T12	1
valid_sources[0x24]	22712	1			T20	2		T37	3		T9	3
valid_sources[0x25]	21782	1			T21	4		T4	3		T53	10
valid_sources[0x26]	22309	1			T19	1		T54	2		T37	1
valid_sources[0x27]	21712	1			T54	4		T69	1		T17	1
valid_sources[0x28]	22422	1			T3	1		T19	1		T53	1
valid_sources[0x29]	21119	1			T4	1		T53	3		T9	1
valid_sources[0x2a]	20185	1			T5	1		T15	1		T37	2
valid_sources[0x2b]	22515	1			T4	1		T17	1		T72	2
valid_sources[0x2c]	22147	1			T5	1		T15	1		T37	1
valid_sources[0x2d]	21530	1			T20	1		T12	1		T54	1
valid_sources[0x2e]	21909	1			T19	1		T4	1		T53	1
valid_sources[0x2f]	22769	1			T3	101		T4	1		T17	1
valid_sources[0x30]	20524	1			T37	1		T9	2		T13	1
valid_sources[0x31]	21838	1			T20	2		T4	1		T15	1
valid_sources[0x32]	22960	1			T22	2		T53	1		T12	1
valid_sources[0x33]	20747	1			T19	1		T4	1		T38	2
valid_sources[0x34]	22659	1			T33	2		T69	7		T83	1
valid_sources[0x35]	21124	1			T53	1		T15	2		T69	2
valid_sources[0x36]	20215	1			T4	1		T53	3		T38	1
valid_sources[0x37]	22121	1			T4	1		T5	1		T37	1
valid_sources[0x38]	20907	1			T19	1		T22	5		T53	2
valid_sources[0x39]	21973	1			T53	8		T11	24		T38	1
valid_sources[0x3a]	21094	1			T19	1		T22	1		T12	1
valid_sources[0x3b]	21749	1			T53	2		T11	11		T5	1
valid_sources[0x3c]	21925	1			T20	1		T22	1		T4	1
valid_sources[0x3d]	22247	1			T4	1		T53	1		T11	22
valid_sources[0x3e]	21896	1			T12	1		T17	2		T113	1
valid_sources[0x3f]	20494	1			T4	2		T5	1		T15	1
valid_sources[0x40]	22916	1			T15	1		T9	1		T13	1
valid_sources[0x41]	23562	1			T53	1		T37	1		T17	2
valid_sources[0x42]	24533	1			T22	2		T53	8		T11	39
valid_sources[0x43]	23097	1			T22	1		T53	1		T12	1
valid_sources[0x44]	22402	1			T4	1		T11	8		T37	3
valid_sources[0x45]	21440	1			T53	2		T15	1		T37	1
valid_sources[0x46]	21862	1			T69	1		T17	1		T83	1
valid_sources[0x47]	22378	1			T5	1		T15	4		T37	1
valid_sources[0x48]	20980	1			T53	5		T11	3		T5	1
valid_sources[0x49]	24106	1			T17	1		T39	3		T13	1
valid_sources[0x4a]	22616	1			T61	1		T50	1		T73	1
valid_sources[0x4b]	21737	1			T22	1		T4	1		T17	1
valid_sources[0x4c]	22200	1			T53	1		T54	5		T37	1
valid_sources[0x4d]	21313	1			T53	2		T54	4		T37	1
valid_sources[0x4e]	22428	1			T20	4		T53	17		T72	1
valid_sources[0x4f]	21671	1			T15	1		T17	2		T43	1
valid_sources[0x50]	21928	1			T19	1		T21	5		T5	2
valid_sources[0x51]	21244	1			T19	1		T21	1		T53	1
valid_sources[0x52]	21656	1			T53	1		T5	1		T85	1
valid_sources[0x53]	21178	1			T61	1		T5	2		T37	1
valid_sources[0x54]	22711	1			T4	1		T53	3		T5	1
valid_sources[0x55]	22541	1			T19	1		T53	4		T38	1
valid_sources[0x56]	21614	1			T38	1		T17	2		T72	1
valid_sources[0x57]	21747	1			T38	1		T5	1		T54	4
valid_sources[0x58]	22180	1			T4	1		T69	1		T9	1
valid_sources[0x59]	21025	1			T19	1		T5	1		T72	1
valid_sources[0x5a]	20573	1			T53	2		T54	2		T17	1
valid_sources[0x5b]	20833	1			T20	1		T53	9		T37	2
valid_sources[0x5c]	21572	1			T19	1		T21	2		T4	1
valid_sources[0x5d]	21347	1			T1	1		T4	1		T53	2
valid_sources[0x5e]	23611	1			T85	1		T113	1		T39	1
valid_sources[0x5f]	21279	1			T21	1		T53	7		T15	2
valid_sources[0x60]	19118	1			T20	4		T4	1		T38	1
valid_sources[0x61]	23680	1			T53	2		T54	3		T17	1
valid_sources[0x62]	20546	1			T22	1		T4	1		T12	2
valid_sources[0x63]	22451	1			T38	1		T17	3		T113	1
valid_sources[0x64]	24476	1			T20	2		T37	1		T17	2
valid_sources[0x65]	21336	1			T39	1		T47	1		T298	1
valid_sources[0x66]	21933	1			T53	3		T17	1		T249	2
valid_sources[0x67]	22308	1			T53	7		T15	2		T17	1
valid_sources[0x68]	23043	1			T19	1		T4	1		T11	11
valid_sources[0x69]	23148	1			T21	3		T53	5		T38	1
valid_sources[0x6a]	21576	1			T19	1		T54	2		T69	1
valid_sources[0x6b]	22125	1			T22	4		T12	1		T15	1
valid_sources[0x6c]	22065	1			T15	2		T50	1		T49	1
valid_sources[0x6d]	21547	1			T4	1		T37	1		T298	1
valid_sources[0x6e]	21751	1			T53	1		T54	10		T113	1
valid_sources[0x6f]	21997	1			T33	2		T4	1		T53	4
valid_sources[0x70]	23676	1			T4	2		T53	2		T61	1
valid_sources[0x71]	21813	1			T53	4		T17	1		T52	1
valid_sources[0x72]	21563	1			T19	1		T22	7		T4	1
valid_sources[0x73]	22179	1			T54	5		T37	1		T17	1
valid_sources[0x74]	22782	1			T19	1		T38	1		T61	2
valid_sources[0x75]	22604	1			T20	1		T5	1		T37	2
valid_sources[0x76]	23741	1			T15	1		T17	1		T83	1
valid_sources[0x77]	21926	1			T53	1		T15	3		T37	1
valid_sources[0x78]	22825	1			T19	1		T15	2		T37	1
valid_sources[0x79]	19901	1			T19	1		T53	2		T37	1
valid_sources[0x7a]	21116	1			T19	1		T20	7		T17	1
valid_sources[0x7b]	20814	1			T22	1		T4	1		T54	1
valid_sources[0x7c]	21411	1			T21	2		T53	3		T5	1
valid_sources[0x7d]	20530	1			T54	1		T43	2		T39	1
valid_sources[0x7e]	21981	1			T38	1		T15	3		T37	1
valid_sources[0x7f]	23009	1			T15	1		T37	2		T72	1
valid_sources[0x80]	23183	1			T53	1		T37	2		T69	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1263222

1

T1

1

T2

3

T3

3

values[0x0]

all_enables

biggest_size

1873489

1

T1

7

T2

6

T3

31

values[0x1]

all_enables

biggest_size

1869605

1

T1

3

T2

5

T3

35