Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2555	1			T3	4		T7	18		T20	2
non_zero_bins[1]	1865	1			T3	1		T7	1		T20	1
zero	9130	1			T1	5		T2	4		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	514	1			T20	1		T53	3		T104	1
uni	3574	1			T7	1		T20	1		T21	1
gen	4370	1			T1	2		T2	1		T3	3
res	797	1			T3	4		T7	2		T8	2
ins	4295	1			T1	3		T2	3		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8883

1

T1

3

T2

3

T7

19

mubi_true

4667

1

T1

2

T2

1

T3

9

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

16

1

T38

1

T69

1

T296

1

pass

13534

1

T1

5

T2

4

T3

9

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	110	1			T47	1		T34	1		T36	3
upd	non_zero_bins[0]	pass	mubi_true	120	1			T297	1		T35	2		T36	3
upd	non_zero_bins[1]	pass	mubi_false	89	1			T53	2		T73	1		T34	1
upd	non_zero_bins[1]	pass	mubi_true	89	1			T20	1		T53	1		T104	1
upd	zero	pass	mubi_false	51	1			T103	1		T36	1		T223	1
upd	zero	pass	mubi_true	55	1			T41	1		T34	1		T36	1
uni	zero	pass	mubi_false	2626	1			T7	1		T20	1		T21	1
uni	zero	pass	mubi_true	948	1			T249	1		T39	1		T96	1
gen	non_zero_bins[0]	pass	mubi_false	465	1			T7	15		T20	1		T15	3
gen	non_zero_bins[0]	pass	mubi_true	501	1			T3	3		T7	1		T53	1
gen	non_zero_bins[1]	pass	mubi_false	368	1			T53	1		T249	1		T73	1
gen	non_zero_bins[1]	pass	mubi_true	349	1			T54	1		T17	11		T47	1
gen	zero	fail	mubi_false	15	1			T38	1		T69	1		T296	1
gen	zero	pass	mubi_false	1907	1			T1	2		T18	1		T21	1
gen	zero	pass	mubi_true	765	1			T2	1		T19	2		T21	2
res	non_zero_bins[0]	pass	mubi_false	178	1			T7	2		T85	2		T298	1
res	non_zero_bins[0]	pass	mubi_true	204	1			T8	1		T70	2		T17	2
res	non_zero_bins[1]	pass	mubi_false	125	1			T51	1		T16	2		T76	1
res	non_zero_bins[1]	pass	mubi_true	111	1			T8	1		T15	2		T10	2
res	zero	fail	mubi_false	1	1			T163	1		-	-		-	-
res	zero	pass	mubi_false	93	1			T109	1		T44	2		T68	4
res	zero	pass	mubi_true	85	1			T3	4		T52	4		T66	5
ins	non_zero_bins[0]	pass	mubi_false	477	1			T53	2		T54	1		T52	1
ins	non_zero_bins[0]	pass	mubi_true	500	1			T3	1		T20	1		T53	2
ins	non_zero_bins[1]	pass	mubi_false	366	1			T7	1		T8	2		T15	1
ins	non_zero_bins[1]	pass	mubi_true	368	1			T3	1		T37	1		T39	2
ins	zero	pass	mubi_false	2012	1			T1	1		T2	3		T18	1
ins	zero	pass	mubi_true	572	1			T1	2		T19	1		T21	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded