Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T19
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T18

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T19,T20
1	0	Covered	T3,T8,T22
1	1	Covered	T3,T7,T8

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T19,T21,T22
1	0	Covered	T1,T2,T4

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T19,T21,T22
1	Covered	T1,T2,T4

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T19,T21,T22
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T19
1	Covered	T1,T2,T4

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T7,T8
AutoCaptGenCnt	143	Covered	T3,T7,T8
AutoCaptReseedCnt	141	Covered	T3,T7,T8
AutoDispatch	125	Covered	T3,T7,T8
AutoFirstAckWait	119	Covered	T3,T7,T8
AutoLoadIns	69	Covered	T3,T7,T8
AutoSendGenCmd	150	Covered	T3,T7,T8
AutoSendReseedCmd	162	Covered	T3,T7,T8
BootDone	98	Covered	T1,T2,T18
BootGenAckWait	90	Covered	T1,T2,T18
BootInsAckWait	80	Covered	T1,T2,T18
BootLoadGen	85	Covered	T1,T2,T18
BootLoadIns	65	Covered	T1,T2,T18
BootLoadUni	102	Covered	T1,T21,T33
BootPulse	94	Covered	T1,T2,T18
BootUniAckWait	107	Covered	T21,T33,T71
Error	188	Covered	T1,T2,T4
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T19,T21,T22
SWPortMode	74	Covered	T7,T19,T20

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T7,T8
AutoAckWait->Error	188	Covered	T120,T121,T122
AutoAckWait->Idle	211	Covered	T3,T8,T52
AutoAckWait->RejectCsrngEntropy	188	Covered	T69,T83,T82
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T7,T8
AutoCaptGenCnt->Error	188	Covered	T123,T124,T125
AutoCaptGenCnt->Idle	211	Covered	T126,T127
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T128,T129,T130
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T7,T8
AutoCaptReseedCnt->Error	188	Covered	T131,T132,T133
AutoCaptReseedCnt->Idle	211	Covered	T134,T135,T136
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T137,T138,T139
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T7,T8
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T7,T8
AutoDispatch->Error	188	Covered	T140,T141,T142
AutoDispatch->Idle	138	Covered	T7,T15,T70
AutoDispatch->RejectCsrngEntropy	188	Covered	T143,T144,T145
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T7,T8
AutoFirstAckWait->Error	188	Covered	T146,T147
AutoFirstAckWait->Idle	211	Covered	T148,T149,T150
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T151,T152,T153
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T7,T8
AutoLoadIns->Error	188	Covered	T5,T6,T59
AutoLoadIns->Idle	211	Covered	T4,T38,T5
AutoLoadIns->RejectCsrngEntropy	188	Covered	T108,T78,T154
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T7,T8
AutoSendGenCmd->Error	188	Covered	T155,T156,T157
AutoSendGenCmd->Idle	211	Covered	T158
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T111,T159,T160
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T7,T8
AutoSendReseedCmd->Error	188	Covered	T161,T110,T162
AutoSendReseedCmd->Idle	211	Covered	T3,T52,T66
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T109,T163,T164
BootDone->BootLoadUni	102	Covered	T1,T21,T33
BootDone->Error	188	Covered	T94,T165,T166
BootDone->Idle	211	Covered	T40,T97,T167
BootDone->RejectCsrngEntropy	188	Covered	T33,T168,T169
BootGenAckWait->BootPulse	94	Covered	T1,T2,T18
BootGenAckWait->Error	188	Covered	T170
BootGenAckWait->Idle	211	Covered	T46,T171,T84
BootGenAckWait->RejectCsrngEntropy	188	Covered	T38,T113,T49
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T18
BootInsAckWait->Error	188	Covered	T61,T57,T172
BootInsAckWait->Idle	211	Covered	T1,T2,T61
BootInsAckWait->RejectCsrngEntropy	188	Covered	T19,T42,T43
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T18
BootLoadGen->Error	188	Covered	T173,T174
BootLoadGen->Idle	211	Covered	T175,T176,T177
BootLoadGen->RejectCsrngEntropy	188	Covered	T22,T178,T179
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T18
BootLoadIns->Error	188	Covered	T58,T180,T181
BootLoadIns->Idle	211	Covered	T182,T183,T184
BootLoadIns->RejectCsrngEntropy	188	Covered	T72,T77,T185
BootLoadUni->BootUniAckWait	107	Covered	T21,T33,T71
BootLoadUni->Error	188	Covered	T1,T186
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T80,T187,T188
BootPulse->BootDone	98	Covered	T1,T2,T18
BootPulse->Error	188	Covered	T105,T56
BootPulse->Idle	211	Covered	T189,T190,T191
BootPulse->RejectCsrngEntropy	188	Covered	T192,T193,T194
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T33,T72,T113
BootUniAckWait->RejectCsrngEntropy	188	Covered	T21,T71,T195
Idle->AutoLoadIns	69	Covered	T3,T7,T8
Idle->BootLoadIns	65	Covered	T1,T2,T18
Idle->Error	188	Covered	T11,T13,T14
Idle->RejectCsrngEntropy	188	Covered	T19,T71,T72
Idle->SWPortMode	74	Covered	T7,T19,T20
RejectCsrngEntropy->Error	188	Covered	T196,T197,T198
RejectCsrngEntropy->Idle	211	Covered	T19,T21,T22
SWPortMode->Error	188	Covered	T11,T12,T62
SWPortMode->Idle	211	Covered	T19,T21,T22
SWPortMode->RejectCsrngEntropy	188	Covered	T21,T22,T33

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T19,T20
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T21,T33
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T18
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T33
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T21,T33,T71
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T21,T33,T71
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T7,T8
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T7,T8
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T7,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T7,T8
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T7,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T15,T70
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T7,T8
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T7,T8
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T7,T8
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T7,T8
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T7,T8
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T8
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T19,T20
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T22
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T11

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T2,T4
1	0	1	-	Not Covered
1	0	0	-	Covered	T19,T21,T22
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	197283639	159492	0	0
FpvSecCmErrorStEscalate_A	197283639	160787	0	0
u_state_regs_A	197243446	197042634	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	159492	0	0
T1	609	302	0	0
T2	1954	1100	0	0
T3	2613	0	0	0
T4	0	1100	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	160787	0	0
T1	609	303	0	0
T2	1954	1101	0	0
T3	2613	0	0	0
T4	0	1101	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197243446	197042634	0	0
T1	421	284	0	0
T2	1770	1607	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0