Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	95.71	100.00	100.00		78.57	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.71	100.00	100.00		78.57	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T18
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T189,T190,T199
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T18
DataWait->AckPls	80	Covered	T3,T7,T18
DataWait->Disabled	107	Covered	T200,T99,T84
DataWait->Error	99	Covered	T1,T2,T5
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T7,T18
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T7,T18
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T3,T7,T18
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T1,T11,T61

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1380985473	1128544	0	0
FpvSecCmErrorStEscalate_A	1380985473	1137609	0	0
u_state_regs_A	1380945280	1379539596	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1380985473	1128544	0	0
T1	4263	2064	0	0
T2	13678	8050	0	0
T3	18291	0	0	0
T4	0	8050	0	0
T5	0	4536	0	0
T6	0	2534	0	0
T7	32928	0	0	0
T8	22645	0	0	0
T11	0	118398	0	0
T12	0	7875	0	0
T18	7833	0	0	0
T19	13860	0	0	0
T20	12796	0	0	0
T21	20146	0	0	0
T22	10850	0	0	0
T55	0	4494	0	0
T61	0	7895	0	0
T62	0	8091	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1380985473	1137609	0	0
T1	4263	2071	0	0
T2	13678	8057	0	0
T3	18291	0	0	0
T4	0	8057	0	0
T5	0	4543	0	0
T6	0	2541	0	0
T7	32928	0	0	0
T8	22645	0	0	0
T11	0	120218	0	0
T12	0	7882	0	0
T18	7833	0	0	0
T19	13860	0	0	0
T20	12796	0	0	0
T21	20146	0	0	0
T22	10850	0	0	0
T55	0	4501	0	0
T61	0	7902	0	0
T62	0	8098	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1380945280	1379539596	0	0
T1	4075	3116	0	0
T2	13494	12353	0	0
T3	18291	17612	0	0
T7	32928	32249	0	0
T8	22645	21980	0	0
T18	7833	7322	0	0
T19	13860	13237	0	0
T20	12796	12334	0	0
T21	20146	19579	0	0
T22	10850	10416	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	11	78.57
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T33,T12,T38
DataWait	75	Covered	T33,T12,T38
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T33,T12,T38
DataWait->AckPls	80	Covered	T33,T12,T38
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T105,T204,T205
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T33,T12,T38
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T33,T12,T38
Idle	-	1	0	-	Covered	T33,T12,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T33,T12,T38
DataWait	-	-	-	0	Covered	T38,T46,T39
AckPls	-	-	-	-	Covered	T33,T12,T38
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T20,T21
DataWait	75	Covered	T2,T7,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T20,T21
DataWait->AckPls	80	Covered	T7,T20,T21
DataWait->Disabled	107	Covered	T200,T99,T177
DataWait->Error	99	Covered	T2,T5,T56
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T7,T20
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T12,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T20,T21
Idle	-	1	0	-	Covered	T2,T7,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T20,T21
DataWait	-	-	-	0	Covered	T2,T7,T20
AckPls	-	-	-	-	Covered	T7,T20,T21
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T1,T11,T61

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	159592	0	0
FpvSecCmErrorStEscalate_A	197283639	160887	0	0
u_state_regs_A	197243446	197042634	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	159592	0	0
T1	609	252	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1085	0	0
T62	0	1113	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	160887	0	0
T1	609	253	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1086	0	0
T62	0	1114	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197243446	197042634	0	0
T1	421	284	0	0
T2	1770	1607	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T37,T17
DataWait	75	Covered	T7,T37,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T37,T17
DataWait->AckPls	80	Covered	T7,T37,T17
DataWait->Disabled	107	Covered	T206,T207,T126
DataWait->Error	99	Covered	T6,T165,T140
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T37,T17
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T37,T17
Idle	-	1	0	-	Covered	T7,T37,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T37,T17
DataWait	-	-	-	0	Covered	T7,T37,T17
AckPls	-	-	-	-	Covered	T7,T37,T17
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T33,T37
DataWait	75	Covered	T7,T33,T37
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T189
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T33,T37
DataWait->AckPls	80	Covered	T7,T33,T37
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T186,T173,T121
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T33,T37
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T33,T37
Idle	-	1	0	-	Covered	T7,T33,T37
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T33,T37
DataWait	-	-	-	0	Covered	T7,T33,T37
AckPls	-	-	-	-	Covered	T7,T33,T37
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T37,T17,T40
DataWait	75	Covered	T37,T17,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T37,T17,T40
DataWait->AckPls	80	Covered	T37,T17,T40
DataWait->Disabled	107	Covered	T84,T87,T175
DataWait->Error	99	Covered	T208
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T37,T17,T40
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T37,T17,T40
Idle	-	1	0	-	Covered	T37,T17,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T37,T17,T40
DataWait	-	-	-	0	Covered	T37,T17,T40
AckPls	-	-	-	-	Covered	T37,T17,T40
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T7,T18
DataWait	75	Covered	T1,T3,T7
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T199
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T7,T18
DataWait->AckPls	80	Covered	T3,T7,T18
DataWait->Disabled	107	Covered	T209
DataWait->Error	99	Covered	T1,T196,T120
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T3,T7
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T2,T4,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T7,T18
Idle	-	1	0	-	Covered	T1,T3,T7
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T7,T18
DataWait	-	-	-	0	Covered	T1,T3,T7
AckPls	-	-	-	-	Covered	T3,T7,T18
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T37,T39
DataWait	75	Covered	T7,T37,T39
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T2,T4
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T190
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T37,T39
DataWait->AckPls	80	Covered	T7,T37,T39
DataWait->Disabled	107	Covered	T210,T211,T212
DataWait->Error	99	Covered	T213,T198,T155
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T11,T13,T14
EndPointClear->Disabled	107	Covered	T201,T202,T182
EndPointClear->Error	99	Covered	T11,T13,T203
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T37,T39
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T37,T39
Idle	-	1	0	-	Covered	T7,T37,T39
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T37,T39
DataWait	-	-	-	0	Covered	T7,T37,T39
AckPls	-	-	-	-	Covered	T7,T37,T39
Error	-	-	-	-	Covered	T1,T2,T4
default	-	-	-	-	Covered	T11,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	197283639	161492	0	0
FpvSecCmErrorStEscalate_A	197283639	162787	0	0
u_state_regs_A	197283639	197082827	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	161492	0	0
T1	609	302	0	0
T2	1954	1150	0	0
T3	2613	0	0	0
T4	0	1150	0	0
T5	0	648	0	0
T6	0	362	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	16914	0	0
T12	0	1125	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	642	0	0
T61	0	1135	0	0
T62	0	1163	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	162787	0	0
T1	609	303	0	0
T2	1954	1151	0	0
T3	2613	0	0	0
T4	0	1151	0	0
T5	0	649	0	0
T6	0	363	0	0
T7	4704	0	0	0
T8	3235	0	0	0
T11	0	17174	0	0
T12	0	1126	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	0	0	0
T55	0	643	0	0
T61	0	1136	0	0
T62	0	1164	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0