Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T26,T28,T29
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T31,T32
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	393754272	1043373	0	0
DepthKnown_A	394567278	394165654	0	0
RvalidKnown_A	394567278	394165654	0	0
WreadyKnown_A	394567278	394165654	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	394141954	1144185	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	393754272	1043373	0	0
T3	5226	3221	0	0
T4	940	522	0	0
T5	0	251	0	0
T7	9408	4986	0	0
T8	6470	4150	0	0
T15	0	1915	0	0
T18	2238	0	0	0
T19	3960	0	0	0
T20	3656	0	0	0
T21	5756	0	0	0
T22	3100	69	0	0
T33	4634	0	0	0
T38	0	275	0	0
T69	0	1079	0	0
T70	0	8972	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394567278	394165654	0	0
T1	1218	944	0	0
T2	3908	3582	0	0
T3	5226	5032	0	0
T7	9408	9214	0	0
T8	6470	6280	0	0
T18	2238	2092	0	0
T19	3960	3782	0	0
T20	3656	3524	0	0
T21	5756	5594	0	0
T22	3100	2976	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394567278	394165654	0	0
T1	1218	944	0	0
T2	3908	3582	0	0
T3	5226	5032	0	0
T7	9408	9214	0	0
T8	6470	6280	0	0
T18	2238	2092	0	0
T19	3960	3782	0	0
T20	3656	3524	0	0
T21	5756	5594	0	0
T22	3100	2976	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394567278	394165654	0	0
T1	1218	944	0	0
T2	3908	3582	0	0
T3	5226	5032	0	0
T7	9408	9214	0	0
T8	6470	6280	0	0
T18	2238	2092	0	0
T19	3960	3782	0	0
T20	3656	3524	0	0
T21	5756	5594	0	0
T22	3100	2976	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	394141954	1144185	0	0
T1	1218	293	0	0
T2	3908	279	0	0
T3	5226	3221	0	0
T4	0	2401	0	0
T5	0	3485	0	0
T7	9408	4986	0	0
T8	6470	4150	0	0
T18	2238	0	0	0
T19	3960	0	0	0
T20	3656	0	0	0
T21	5756	0	0	0
T22	3100	69	0	0
T38	0	275	0	0
T61	0	2282	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T26,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T26,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T88,T89
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196877136	515262	0	0
DepthKnown_A	197283639	197082827	0	0
RvalidKnown_A	197283639	197082827	0	0
WreadyKnown_A	197283639	197082827	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	197070977	565454	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196877136	515262	0	0
T3	2613	1523	0	0
T4	470	251	0	0
T5	0	67	0	0
T7	4704	2479	0	0
T8	3235	2044	0	0
T15	0	953	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	23	0	0
T33	2317	0	0	0
T38	0	131	0	0
T69	0	496	0	0
T70	0	4465	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	197070977	565454	0	0
T1	609	149	0	0
T2	1954	141	0	0
T3	2613	1523	0	0
T4	0	1133	0	0
T5	0	1673	0	0
T7	4704	2479	0	0
T8	3235	2044	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	23	0	0
T38	0	131	0	0
T61	0	1143	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T32,T90
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	196877136	528111	0	0
DepthKnown_A	197283639	197082827	0	0
RvalidKnown_A	197283639	197082827	0	0
WreadyKnown_A	197283639	197082827	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	197070977	578731	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196877136	528111	0	0
T3	2613	1698	0	0
T4	470	271	0	0
T5	0	184	0	0
T7	4704	2507	0	0
T8	3235	2106	0	0
T15	0	962	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	46	0	0
T33	2317	0	0	0
T38	0	144	0	0
T69	0	583	0	0
T70	0	4507	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197283639	197082827	0	0
T1	609	472	0	0
T2	1954	1791	0	0
T3	2613	2516	0	0
T7	4704	4607	0	0
T8	3235	3140	0	0
T18	1119	1046	0	0
T19	1980	1891	0	0
T20	1828	1762	0	0
T21	2878	2797	0	0
T22	1550	1488	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	197070977	578731	0	0
T1	609	144	0	0
T2	1954	138	0	0
T3	2613	1698	0	0
T4	0	1268	0	0
T5	0	1812	0	0
T7	4704	2507	0	0
T8	3235	2106	0	0
T18	1119	0	0	0
T19	1980	0	0	0
T20	1828	0	0	0
T21	2878	0	0	0
T22	1550	46	0	0
T38	0	144	0	0
T61	0	1139	0	0