Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	139	1			T1	1		T23	1		T44	1
auto_req_mode	136	1			T3	1		T10	1		T11	1
sw_mode	2828	1			T22	1		T5	2		T24	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

319

1

T1

1

T3

1

T10

1

single

81

1

T45

1

T39

1

T43

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1308	1			T1	1		T3	1		T22	1
auto[2]	90	1			T319	1		T231	42		T320	1
auto[3]	63	1			T83	1		T286	1		T321	1
auto[4]	72	1			T102	15		T84	1		T322	1
auto[5]	158	1			T54	5		T43	1		T50	1
auto[6]	150	1			T11	1		T229	83		T323	1
auto[7]	1262	1			T10	1		T44	1		T45	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	85	1			T1	1		T23	1		T63	1
auto[1]	auto_req_mode	78	1			T3	1		T88	1		T93	1
auto[1]	sw_mode	1145	1			T22	1		T5	2		T24	1
auto[2]	boot_req_mode	3	1			T319	1		T324	1		T325	1
auto[2]	auto_req_mode	2	1			T326	1		T327	1		-	-
auto[2]	sw_mode	85	1			T231	42		T320	1		T328	1
auto[3]	boot_req_mode	5	1			T329	1		T330	1		T331	1
auto[3]	auto_req_mode	4	1			T83	1		T321	1		T332	1
auto[3]	sw_mode	54	1			T286	1		T333	49		T334	1
auto[4]	boot_req_mode	3	1			T335	1		T336	1		T337	1
auto[4]	auto_req_mode	5	1			T84	1		T338	1		T339	1
auto[4]	sw_mode	64	1			T102	15		T322	1		T232	40
auto[5]	boot_req_mode	4	1			T43	1		T50	1		T73	1
auto[5]	auto_req_mode	4	1			T340	1		T341	1		T342	1
auto[5]	sw_mode	150	1			T54	5		T287	1		T235	68
auto[6]	boot_req_mode	5	1			T323	1		T343	1		T344	1
auto[6]	auto_req_mode	3	1			T11	1		T345	1		T346	1
auto[6]	sw_mode	142	1			T229	83		T347	1		T348	1
auto[7]	boot_req_mode	34	1			T44	1		T41	1		T46	1
auto[7]	auto_req_mode	40	1			T10	1		T20	1		T12	1
auto[7]	sw_mode	1188	1			T45	1		T40	1		T36	49