Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64




Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cs_cmds_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 19 0 19 100.00
Crosses 34 0 34 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cr_generate_intended 9 0 9 100.00 100 1 1 0
cr_instantiate_intended 9 0 9 100.00 100 1 1 0
cr_reseed_intended 8 0 8 100.00 100 1 1 0
cr_update_intended 2 0 2 100.00 100 1 1 0
cr_uninstantiate_intended 1 0 1 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAME   COUNT   STATUS   
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[INS] 4284 1 T1 2 T2 2 T3 2
auto[RES] 1093 1 T1 1 T3 2 T10 1
auto[GEN] 4392 1 T1 2 T2 4 T3 2
auto[UPD] 553 1 T40 1 T55 2 T36 12
auto[UNI] 3520 1 T1 1 T22 1 T10 2



Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
some_cmd_data 4486 1 T1 3 T3 3 T10 4
no_cmd_data 9362 1 T1 3 T2 6 T3 3



Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
sw_cmd_req 12060 1 T1 4 T2 3 T3 2
reseed_cmd 589 1 T3 2 T10 1 T4 1
generate_cmd 545 1 T3 2 T10 1 T4 1
boot_gen_cmd 379 1 T1 1 T2 2 T4 2
boot_ins_cmd 275 1 T1 1 T2 1 T4 2



Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
true 4571 1 T1 1 T2 4 T3 1
false 9277 1 T1 5 T2 2 T3 5



Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
multiple 1426 1 T1 4 T2 1 T3 3
one 2605 1 T2 3 T3 2 T22 1



Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
sw_mode 11107 1 T1 4 T22 3 T10 2
boot_mode 714 1 T1 2 T2 3 T4 6
auto_mode 2027 1 T2 3 T3 6 T10 4



Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmd   cp_clen   cp_glen   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmd   cp_clen   cp_glen   cp_mode   cp_cmd_src   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 180 1 T1 1 T11 1 T62 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 155 1 T11 1 T7 2 T20 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 58 1 T10 1 T349 1 T350 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 132 1 T9 2 T16 2 T12 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 43 1 T46 1 T40 1 T351 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 66 1 T1 1 T44 1 T63 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 33 1 T10 1 T8 2 T49 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1462 1 T22 1 T5 2 T24 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 169 1 T3 2 T27 1 T7 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded



Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmd   cp_clen   cp_flags   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmd   cp_clen   cp_flags   cp_mode   cp_cmd_src   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[INS] some_cmd_data true sw_mode sw_cmd_req 814 1 T24 1 T54 2 T55 4
auto[INS] some_cmd_data true auto_mode sw_cmd_req 59 1 T11 1 T49 1 T21 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 828 1 T1 1 T62 1 T63 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 101 1 T3 1 T10 1 T11 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 188 1 T44 1 T40 1 T55 2
auto[INS] no_cmd_data true auto_mode sw_cmd_req 224 1 T2 1 T27 1 T28 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1647 1 T22 1 T5 2 T41 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 141 1 T2 1 T4 2 T23 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 148 1 T3 1 T27 1 T7 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded



Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmd   cp_clen   cp_flags   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmd   cp_clen   cp_flags   cp_mode   cp_cmd_src   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[RES] some_cmd_data true sw_mode sw_cmd_req 204 1 T24 1 T45 1 T55 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 124 1 T10 1 T11 1 T8 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 179 1 T1 1 T44 1 T62 1
auto[RES] some_cmd_data false auto_mode reseed_cmd 133 1 T3 2 T7 2 T8 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 53 1 T36 1 T37 2 T38 1
auto[RES] no_cmd_data true auto_mode reseed_cmd 50 1 T49 1 T156 1 T72 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 50 1 T36 3 T37 2 T38 1
auto[RES] no_cmd_data false auto_mode reseed_cmd 226 1 T27 1 T7 2 T8 2


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded



Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmd   cp_clen   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmd   cp_clen   cp_mode   cp_cmd_src   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[UPD] some_cmd_data sw_mode sw_cmd_req 434 1 T40 1 T55 1 T36 10
auto[UPD] no_cmd_data sw_mode sw_cmd_req 101 1 T55 1 T36 2 T37 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded



Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 1 0 1 100.00
Automatically Generated Cross Bins 1 0 1 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmd   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 3504 1 T1 1 T22 1 T10 1


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded



Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmd   cp_mode   cp_cmd_src   COUNT   STATUS   
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmd   cp_mode   cp_cmd_src   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[INS] auto_mode sw_cmd_req 532 1 T2 1 T3 2 T10 1
auto[RES] auto_mode sw_cmd_req 18 1 T20 1 T83 1 T21 1
auto[GEN] auto_mode sw_cmd_req 415 1 T2 2 T27 2 T28 2
auto[UPD] auto_mode sw_cmd_req 18 1 T13 1 T352 1 T252 1
auto[UNI] auto_mode sw_cmd_req 16 1 T10 1 T12 1 T346 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded