Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	665760	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5385617

1

T1

45

T2

24

T3

64

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1601094	1			T1	80		T2	27		T3	18
values[0x0]	2057376	1			T1	18		T2	14		T3	31
values[0x1]	2392907	1			T1	27		T2	12		T3	38

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	330079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5721298

1

T1

73

T2

34

T3

70

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23608	1			T11	1		T55	3		T36	273
valid_sources[0x01]	24397	1			T24	1		T63	3		T45	1
valid_sources[0x02]	23725	1			T11	1		T45	2		T41	2
valid_sources[0x03]	23505	1			T44	1		T62	1		T41	2
valid_sources[0x04]	22770	1			T45	1		T8	1		T46	51
valid_sources[0x05]	23472	1			T55	1		T36	236		T20	3
valid_sources[0x06]	25565	1			T11	2		T45	1		T55	3
valid_sources[0x07]	23388	1			T27	1		T44	1		T63	3
valid_sources[0x08]	25417	1			T11	2		T28	2		T41	1
valid_sources[0x09]	23045	1			T5	1		T45	2		T8	1
valid_sources[0x0a]	23260	1			T2	6		T11	1		T62	2
valid_sources[0x0b]	24723	1			T1	1		T52	5		T6	4
valid_sources[0x0c]	24329	1			T5	1		T11	1		T44	1
valid_sources[0x0d]	22990	1			T1	1		T11	1		T44	1
valid_sources[0x0e]	23376	1			T11	1		T27	8		T41	1
valid_sources[0x0f]	24359	1			T5	2		T44	1		T45	1
valid_sources[0x10]	24805	1			T1	2		T44	1		T52	1
valid_sources[0x11]	24940	1			T1	2		T27	2		T44	2
valid_sources[0x12]	24013	1			T45	1		T42	4		T55	4
valid_sources[0x13]	24726	1			T1	1		T24	1		T11	1
valid_sources[0x14]	23663	1			T27	1		T62	2		T63	1
valid_sources[0x15]	25518	1			T5	1		T23	1		T52	1
valid_sources[0x16]	24627	1			T1	1		T24	2		T11	1
valid_sources[0x17]	23128	1			T11	1		T27	1		T44	3
valid_sources[0x18]	24183	1			T27	1		T63	1		T41	2
valid_sources[0x19]	23510	1			T2	1		T11	1		T52	1
valid_sources[0x1a]	25536	1			T1	3		T24	4		T28	8
valid_sources[0x1b]	21550	1			T1	1		T2	4		T63	1
valid_sources[0x1c]	25307	1			T5	1		T11	1		T53	1
valid_sources[0x1d]	22879	1			T27	1		T63	2		T45	2
valid_sources[0x1e]	23042	1			T11	1		T28	2		T52	2
valid_sources[0x1f]	21985	1			T1	2		T27	2		T45	1
valid_sources[0x20]	23697	1			T5	1		T11	1		T44	1
valid_sources[0x21]	24742	1			T1	1		T5	3		T44	1
valid_sources[0x22]	24205	1			T5	4		T24	1		T44	4
valid_sources[0x23]	23106	1			T81	1		T15	2		T55	2
valid_sources[0x24]	24614	1			T5	2		T24	6		T63	2
valid_sources[0x25]	22569	1			T11	1		T27	1		T63	1
valid_sources[0x26]	24674	1			T1	2		T23	1		T41	1
valid_sources[0x27]	22553	1			T1	2		T3	9		T45	1
valid_sources[0x28]	22744	1			T5	1		T11	1		T44	1
valid_sources[0x29]	24144	1			T63	2		T45	1		T41	1
valid_sources[0x2a]	22246	1			T45	1		T41	1		T54	7
valid_sources[0x2b]	24481	1			T5	3		T63	2		T45	1
valid_sources[0x2c]	25528	1			T62	1		T52	1		T45	3
valid_sources[0x2d]	22012	1			T1	1		T27	1		T45	1
valid_sources[0x2e]	23856	1			T3	1		T45	1		T55	7
valid_sources[0x2f]	24698	1			T1	2		T3	4		T62	2
valid_sources[0x30]	25018	1			T22	5		T45	1		T8	1
valid_sources[0x31]	22836	1			T5	1		T42	4		T55	2
valid_sources[0x32]	23598	1			T45	2		T41	1		T42	1
valid_sources[0x33]	23072	1			T5	5		T62	1		T55	4
valid_sources[0x34]	25391	1			T1	1		T63	2		T41	1
valid_sources[0x35]	21470	1			T5	1		T45	2		T8	4
valid_sources[0x36]	23417	1			T44	1		T45	1		T41	1
valid_sources[0x37]	24557	1			T1	1		T11	1		T63	2
valid_sources[0x38]	26023	1			T1	3		T27	1		T62	3
valid_sources[0x39]	25032	1			T2	1		T28	3		T45	1
valid_sources[0x3a]	22191	1			T45	2		T41	2		T8	1
valid_sources[0x3b]	22994	1			T2	3		T11	1		T44	1
valid_sources[0x3c]	23935	1			T44	1		T62	2		T45	1
valid_sources[0x3d]	22936	1			T22	1		T45	1		T55	1
valid_sources[0x3e]	23637	1			T1	1		T3	9		T5	2
valid_sources[0x3f]	22632	1			T24	11		T27	1		T63	4
valid_sources[0x40]	22096	1			T55	5		T36	202		T20	1
valid_sources[0x41]	24372	1			T4	8		T5	2		T24	6
valid_sources[0x42]	23090	1			T5	1		T23	1		T44	1
valid_sources[0x43]	24077	1			T2	3		T11	3		T62	1
valid_sources[0x44]	23704	1			T1	1		T5	3		T27	1
valid_sources[0x45]	22488	1			T1	1		T5	1		T45	1
valid_sources[0x46]	26317	1			T3	1		T24	2		T27	1
valid_sources[0x47]	23646	1			T62	2		T45	1		T41	2
valid_sources[0x48]	24458	1			T5	3		T28	6		T7	1
valid_sources[0x49]	22542	1			T5	2		T62	3		T63	2
valid_sources[0x4a]	23677	1			T5	1		T44	2		T52	1
valid_sources[0x4b]	24040	1			T11	1		T44	1		T45	2
valid_sources[0x4c]	24095	1			T22	2		T5	2		T45	1
valid_sources[0x4d]	22114	1			T44	1		T62	11		T63	1
valid_sources[0x4e]	23431	1			T1	2		T24	3		T62	6
valid_sources[0x4f]	23444	1			T5	1		T63	4		T45	1
valid_sources[0x50]	23471	1			T54	2		T55	4		T36	248
valid_sources[0x51]	24299	1			T62	7		T63	1		T81	2
valid_sources[0x52]	22925	1			T11	2		T27	1		T45	2
valid_sources[0x53]	22836	1			T1	4		T27	3		T45	2
valid_sources[0x54]	23645	1			T22	2		T5	1		T7	2
valid_sources[0x55]	22855	1			T1	3		T8	1		T54	1
valid_sources[0x56]	24501	1			T1	1		T5	1		T54	1
valid_sources[0x57]	23456	1			T27	1		T62	9		T45	1
valid_sources[0x58]	23981	1			T63	6		T53	1		T45	2
valid_sources[0x59]	25164	1			T1	2		T2	3		T52	1
valid_sources[0x5a]	23289	1			T3	1		T24	4		T63	3
valid_sources[0x5b]	24208	1			T22	10		T11	1		T52	1
valid_sources[0x5c]	23605	1			T5	2		T52	2		T45	1
valid_sources[0x5d]	23199	1			T5	2		T11	1		T63	1
valid_sources[0x5e]	25334	1			T3	2		T22	2		T5	2
valid_sources[0x5f]	23651	1			T45	2		T55	3		T36	248
valid_sources[0x60]	23231	1			T22	1		T5	1		T27	1
valid_sources[0x61]	23547	1			T1	3		T5	2		T11	1
valid_sources[0x62]	23911	1			T1	3		T3	7		T5	4
valid_sources[0x63]	24041	1			T5	1		T44	2		T63	2
valid_sources[0x64]	22011	1			T24	2		T11	1		T27	1
valid_sources[0x65]	24374	1			T3	6		T27	1		T62	2
valid_sources[0x66]	22420	1			T45	1		T41	5		T7	1
valid_sources[0x67]	24783	1			T8	1		T55	4		T36	230
valid_sources[0x68]	21677	1			T28	2		T41	1		T54	1
valid_sources[0x69]	23457	1			T1	3		T11	1		T44	1
valid_sources[0x6a]	22317	1			T22	1		T11	1		T44	1
valid_sources[0x6b]	23646	1			T1	1		T45	1		T41	1
valid_sources[0x6c]	23116	1			T27	1		T8	1		T54	1
valid_sources[0x6d]	20961	1			T2	3		T45	1		T55	9
valid_sources[0x6e]	24141	1			T3	4		T5	1		T62	4
valid_sources[0x6f]	24605	1			T5	1		T23	1		T11	2
valid_sources[0x70]	24405	1			T5	1		T24	3		T11	1
valid_sources[0x71]	23356	1			T63	1		T15	3		T55	4
valid_sources[0x72]	25344	1			T1	1		T2	6		T24	1
valid_sources[0x73]	21569	1			T1	1		T2	3		T5	2
valid_sources[0x74]	22466	1			T1	2		T22	2		T5	5
valid_sources[0x75]	25174	1			T5	1		T11	1		T52	1
valid_sources[0x76]	24236	1			T1	3		T3	1		T11	1
valid_sources[0x77]	23069	1			T1	4		T11	5		T27	1
valid_sources[0x78]	22723	1			T5	1		T45	2		T55	2
valid_sources[0x79]	22555	1			T1	1		T62	7		T81	3
valid_sources[0x7a]	23001	1			T5	3		T27	2		T45	1
valid_sources[0x7b]	22276	1			T22	2		T52	1		T8	1
valid_sources[0x7c]	23087	1			T22	2		T52	1		T55	4
valid_sources[0x7d]	22930	1			T45	1		T6	2		T8	2
valid_sources[0x7e]	23714	1			T1	1		T45	1		T42	1
valid_sources[0x7f]	24905	1			T3	3		T28	3		T41	1
valid_sources[0x80]	22390	1			T1	3		T45	1		T41	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1357858

1

T1

3

T2

13

T3

2

values[0x0]

all_enables

biggest_size

2014276

1

T1

17

T2

8

T3

28

values[0x1]

all_enables

biggest_size

2013483

1

T1

25

T2

3

T3

34