Summary for Variable csrng_clen_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for csrng_clen_cp
Bins
| | | | | | | | | | | | |
non_zero_bins[0] |
2588 |
1 |
|
|
T10 |
4 |
|
T24 |
1 |
|
T11 |
7 |
non_zero_bins[1] |
1861 |
1 |
|
|
T1 |
3 |
|
T3 |
5 |
|
T24 |
1 |
zero |
9174 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T3 |
4 |
Summary for Variable csrng_cmd_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for csrng_cmd_cp
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
| | | | | | | | | | | | |
upd |
535 |
1 |
|
|
T40 |
1 |
|
T55 |
2 |
|
T36 |
12 |
uni |
3632 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T22 |
1 |
gen |
4306 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T3 |
3 |
res |
802 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T10 |
2 |
ins |
4348 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Variable csrng_flag_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_flag_cp
Bins
| | | | | | | | | | | | |
mubi_false |
9005 |
1 |
|
|
T1 |
6 |
|
T2 |
3 |
|
T3 |
6 |
mubi_true |
4618 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T3 |
3 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
| | | | | | | | | | | | |
fail |
26 |
1 |
|
|
T42 |
1 |
|
T117 |
1 |
|
T297 |
1 |
pass |
13597 |
1 |
|
|
T1 |
7 |
|
T2 |
6 |
|
T3 |
9 |
Summary for Cross csrng_cmd_cross
Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
| | | | | |
TOTAL |
52 |
24 |
28 |
53.85 |
24 |
Automatically Generated Cross Bins |
52 |
24 |
28 |
53.85 |
24 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for csrng_cmd_cross
Element holes
| | | | | | | |
[upd] |
* |
[fail] |
* |
-- |
-- |
6 |
|
[uni] |
[zero] |
[fail] |
* |
-- |
-- |
2 |
|
[gen , res] |
[non_zero_bins[0] , non_zero_bins[1]] |
[fail] |
* |
-- |
-- |
8 |
|
[ins] |
* |
[fail] |
* |
-- |
-- |
6 |
|
Uncovered bins
csrng_cmd_cp | csrng_clen_cp | csrng_sts | csrng_flag_cp | COUNT | AT LEAST | NUMBER | STATUS |
[gen , res] |
[zero] |
[fail] |
[mubi_true] |
-- |
-- |
2 |
|
Covered bins
| | | | | | | | | | | | | | | |
upd |
non_zero_bins[0] |
pass |
mubi_false |
133 |
1 |
|
|
T55 |
1 |
|
T36 |
4 |
|
T37 |
1 |
upd |
non_zero_bins[0] |
pass |
mubi_true |
120 |
1 |
|
|
T36 |
2 |
|
T37 |
4 |
|
T38 |
3 |
upd |
non_zero_bins[1] |
pass |
mubi_false |
104 |
1 |
|
|
T36 |
1 |
|
T37 |
1 |
|
T38 |
1 |
upd |
non_zero_bins[1] |
pass |
mubi_true |
77 |
1 |
|
|
T40 |
1 |
|
T36 |
3 |
|
T37 |
1 |
upd |
zero |
pass |
mubi_false |
47 |
1 |
|
|
T37 |
1 |
|
T38 |
2 |
|
T50 |
1 |
upd |
zero |
pass |
mubi_true |
54 |
1 |
|
|
T55 |
1 |
|
T36 |
2 |
|
T248 |
1 |
uni |
zero |
pass |
mubi_false |
2707 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T22 |
1 |
uni |
zero |
pass |
mubi_true |
925 |
1 |
|
|
T5 |
1 |
|
T81 |
1 |
|
T54 |
3 |
gen |
non_zero_bins[0] |
pass |
mubi_false |
455 |
1 |
|
|
T11 |
1 |
|
T62 |
1 |
|
T63 |
1 |
gen |
non_zero_bins[0] |
pass |
mubi_true |
500 |
1 |
|
|
T10 |
1 |
|
T11 |
3 |
|
T45 |
1 |
gen |
non_zero_bins[1] |
pass |
mubi_false |
315 |
1 |
|
|
T1 |
1 |
|
T36 |
8 |
|
T37 |
4 |
gen |
non_zero_bins[1] |
pass |
mubi_true |
378 |
1 |
|
|
T36 |
5 |
|
T37 |
4 |
|
T38 |
5 |
gen |
zero |
fail |
mubi_false |
22 |
1 |
|
|
T42 |
1 |
|
T117 |
1 |
|
T297 |
1 |
gen |
zero |
pass |
mubi_false |
1920 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T22 |
1 |
gen |
zero |
pass |
mubi_true |
716 |
1 |
|
|
T2 |
2 |
|
T3 |
3 |
|
T4 |
1 |
res |
non_zero_bins[0] |
pass |
mubi_false |
162 |
1 |
|
|
T62 |
1 |
|
T54 |
1 |
|
T37 |
5 |
res |
non_zero_bins[0] |
pass |
mubi_true |
174 |
1 |
|
|
T10 |
2 |
|
T11 |
2 |
|
T45 |
1 |
res |
non_zero_bins[1] |
pass |
mubi_false |
116 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T44 |
1 |
res |
non_zero_bins[1] |
pass |
mubi_true |
141 |
1 |
|
|
T24 |
1 |
|
T55 |
1 |
|
T43 |
1 |
res |
zero |
fail |
mubi_false |
4 |
1 |
|
|
T298 |
1 |
|
T299 |
1 |
|
T300 |
1 |
res |
zero |
pass |
mubi_false |
107 |
1 |
|
|
T36 |
3 |
|
T37 |
2 |
|
T38 |
1 |
res |
zero |
pass |
mubi_true |
98 |
1 |
|
|
T36 |
1 |
|
T37 |
2 |
|
T38 |
1 |
ins |
non_zero_bins[0] |
pass |
mubi_false |
545 |
1 |
|
|
T10 |
1 |
|
T63 |
1 |
|
T54 |
1 |
ins |
non_zero_bins[0] |
pass |
mubi_true |
499 |
1 |
|
|
T24 |
1 |
|
T11 |
1 |
|
T54 |
1 |
ins |
non_zero_bins[1] |
pass |
mubi_false |
365 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T62 |
1 |
ins |
non_zero_bins[1] |
pass |
mubi_true |
365 |
1 |
|
|
T54 |
1 |
|
T55 |
1 |
|
T36 |
5 |
ins |
zero |
pass |
mubi_false |
2003 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T22 |
1 |
ins |
zero |
pass |
mubi_true |
571 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T27 |
1 |
User Defined Cross Bins for csrng_cmd_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
uni_clen |
0 |
Excluded |