Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
non_zero_bins[0] 2588 1 T10 4 T24 1 T11 7
non_zero_bins[1] 1861 1 T1 3 T3 5 T24 1
zero 9174 1 T1 4 T2 6 T3 4



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
upd 535 1 T40 1 T55 2 T36 12
uni 3632 1 T1 2 T2 1 T22 1
gen 4306 1 T1 2 T2 3 T3 3
res 802 1 T1 1 T3 4 T10 2
ins 4348 1 T1 2 T2 2 T3 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
mubi_false 9005 1 T1 6 T2 3 T3 6
mubi_true 4618 1 T1 1 T2 3 T3 3



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
fail 26 1 T42 1 T117 1 T297 1
pass 13597 1 T1 7 T2 6 T3 9



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cp   csrng_clen_cp   csrng_sts   csrng_flag_cp   COUNT   AT LEAST   NUMBER   STATUS   
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cp   csrng_clen_cp   csrng_sts   csrng_flag_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
upd non_zero_bins[0] pass mubi_false 133 1 T55 1 T36 4 T37 1
upd non_zero_bins[0] pass mubi_true 120 1 T36 2 T37 4 T38 3
upd non_zero_bins[1] pass mubi_false 104 1 T36 1 T37 1 T38 1
upd non_zero_bins[1] pass mubi_true 77 1 T40 1 T36 3 T37 1
upd zero pass mubi_false 47 1 T37 1 T38 2 T50 1
upd zero pass mubi_true 54 1 T55 1 T36 2 T248 1
uni zero pass mubi_false 2707 1 T1 2 T2 1 T22 1
uni zero pass mubi_true 925 1 T5 1 T81 1 T54 3
gen non_zero_bins[0] pass mubi_false 455 1 T11 1 T62 1 T63 1
gen non_zero_bins[0] pass mubi_true 500 1 T10 1 T11 3 T45 1
gen non_zero_bins[1] pass mubi_false 315 1 T1 1 T36 8 T37 4
gen non_zero_bins[1] pass mubi_true 378 1 T36 5 T37 4 T38 5
gen zero fail mubi_false 22 1 T42 1 T117 1 T297 1
gen zero pass mubi_false 1920 1 T1 1 T2 1 T22 1
gen zero pass mubi_true 716 1 T2 2 T3 3 T4 1
res non_zero_bins[0] pass mubi_false 162 1 T62 1 T54 1 T37 5
res non_zero_bins[0] pass mubi_true 174 1 T10 2 T11 2 T45 1
res non_zero_bins[1] pass mubi_false 116 1 T1 1 T3 4 T44 1
res non_zero_bins[1] pass mubi_true 141 1 T24 1 T55 1 T43 1
res zero fail mubi_false 4 1 T298 1 T299 1 T300 1
res zero pass mubi_false 107 1 T36 3 T37 2 T38 1
res zero pass mubi_true 98 1 T36 1 T37 2 T38 1
ins non_zero_bins[0] pass mubi_false 545 1 T10 1 T63 1 T54 1
ins non_zero_bins[0] pass mubi_true 499 1 T24 1 T11 1 T54 1
ins non_zero_bins[1] pass mubi_false 365 1 T1 1 T3 1 T62 1
ins non_zero_bins[1] pass mubi_true 365 1 T54 1 T55 1 T36 5
ins zero pass mubi_false 2003 1 T2 1 T3 1 T22 1
ins zero pass mubi_true 571 1 T1 1 T2 1 T27 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded