Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T23
1	1	Covered	T1,T2,T4

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T27,T28
1	0	Covered	T4,T6,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T6,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T4,T27
1	Covered	T4,T6,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T3,T10,T11
AutoCaptGenCnt	143	Covered	T3,T10,T11
AutoCaptReseedCnt	141	Covered	T3,T10,T11
AutoDispatch	125	Covered	T3,T10,T11
AutoFirstAckWait	119	Covered	T3,T10,T11
AutoLoadIns	69	Covered	T3,T10,T11
AutoSendGenCmd	150	Covered	T3,T10,T11
AutoSendReseedCmd	162	Covered	T3,T10,T11
BootDone	98	Covered	T1,T2,T4
BootGenAckWait	90	Covered	T1,T2,T4
BootInsAckWait	80	Covered	T1,T2,T4
BootLoadGen	85	Covered	T1,T2,T4
BootLoadIns	65	Covered	T1,T2,T4
BootLoadUni	102	Covered	T1,T2,T44
BootPulse	94	Covered	T1,T2,T4
BootUniAckWait	107	Covered	T1,T2,T44
Error	188	Covered	T4,T6,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T27,T28
SWPortMode	74	Covered	T1,T2,T22

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T3,T10,T11
AutoAckWait->Error	188	Covered	T9,T115,T116
AutoAckWait->Idle	211	Covered	T3,T88,T93
AutoAckWait->RejectCsrngEntropy	188	Covered	T27,T117,T108
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T3,T10,T11
AutoCaptGenCnt->Error	188	Covered	T118
AutoCaptGenCnt->Idle	211	Covered	T93,T119,T120
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T90,T82,T121
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T3,T10,T11
AutoCaptReseedCnt->Error	188	Covered	T122,T123,T124
AutoCaptReseedCnt->Idle	211	Covered	T125,T126,T127
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T103,T128,T129
AutoDispatch->AutoCaptGenCnt	143	Covered	T3,T10,T11
AutoDispatch->AutoCaptReseedCnt	141	Covered	T3,T10,T11
AutoDispatch->Error	188	Covered	T130,T131
AutoDispatch->Idle	138	Covered	T3,T10,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T48,T132,T133
AutoFirstAckWait->AutoDispatch	125	Covered	T3,T10,T11
AutoFirstAckWait->Error	188	Covered	T7,T134,T135
AutoFirstAckWait->Idle	211	Covered	T88,T136,T137
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T138,T139,T140
AutoLoadIns->AutoFirstAckWait	119	Covered	T3,T10,T11
AutoLoadIns->Error	188	Covered	T16,T57,T141
AutoLoadIns->Idle	211	Covered	T7,T8,T9
AutoLoadIns->RejectCsrngEntropy	188	Covered	T142,T143,T144
AutoSendGenCmd->AutoAckWait	156	Covered	T3,T10,T11
AutoSendGenCmd->Error	188	Covered	T61,T145,T146
AutoSendGenCmd->Idle	211	Covered	T147,T148,T149
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T150,T151,T152
AutoSendReseedCmd->AutoAckWait	168	Covered	T3,T10,T11
AutoSendReseedCmd->Error	188	Covered	T153,T154,T155
AutoSendReseedCmd->Idle	211	Covered	T156,T157
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T158,T159,T109
BootDone->BootLoadUni	102	Covered	T1,T2,T44
BootDone->Error	188	Not Covered
BootDone->Idle	211	Covered	T39,T67,T160
BootDone->RejectCsrngEntropy	188	Covered	T161,T71,T162
BootGenAckWait->BootPulse	94	Covered	T1,T2,T4
BootGenAckWait->Error	188	Covered	T60,T163
BootGenAckWait->Idle	211	Covered	T4,T23,T164
BootGenAckWait->RejectCsrngEntropy	188	Covered	T52,T42,T89
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T4
BootInsAckWait->Error	188	Covered	T4,T165,T67
BootInsAckWait->Idle	211	Covered	T6,T91,T56
BootInsAckWait->RejectCsrngEntropy	188	Covered	T106,T166,T167
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T4
BootLoadGen->Error	188	Not Covered
BootLoadGen->Idle	211	Covered	T66,T168,T169
BootLoadGen->RejectCsrngEntropy	188	Covered	T170,T171,T172
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T4
BootLoadIns->Error	188	Covered	T173,T174,T175
BootLoadIns->Idle	211	Covered	T176,T177
BootLoadIns->RejectCsrngEntropy	188	Covered	T178,T179,T180
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T44
BootLoadUni->Error	188	Covered	T6,T56,T181
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T104,T182,T183
BootPulse->BootDone	98	Covered	T1,T2,T4
BootPulse->Error	188	Covered	T184
BootPulse->Idle	211	Covered	T47,T185,T186
BootPulse->RejectCsrngEntropy	188	Covered	T28,T187,T188
BootUniAckWait->Error	188	Covered	T189,T190
BootUniAckWait->Idle	112	Covered	T1,T44,T63
BootUniAckWait->RejectCsrngEntropy	188	Covered	T2,T105,T107
Idle->AutoLoadIns	69	Covered	T3,T10,T11
Idle->BootLoadIns	65	Covered	T1,T2,T4
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T2,T28,T106
Idle->SWPortMode	74	Covered	T1,T2,T22
RejectCsrngEntropy->Error	188	Covered	T191,T192
RejectCsrngEntropy->Idle	211	Covered	T2,T27,T28
SWPortMode->Error	188	Covered	T15,T51,T193
SWPortMode->Idle	211	Covered	T2,T5,T27
SWPortMode->RejectCsrngEntropy	188	Covered	T27,T52,T42

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T44
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T23,T52
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T44
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T44
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T44
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T11,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T22
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T99,T100

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T6,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T27,T28
0	-	-	1	Covered	T2,T3,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	207176215	136385	0	0
FpvSecCmErrorStEscalate_A	207176215	137425	0	0
u_state_regs_A	207139068	206964491	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	136385	0	0
T4	2259	655	0	0
T5	2861	0	0	0
T6	0	210	0	0
T7	0	210	0	0
T8	0	730	0	0
T9	0	606	0	0
T11	2459	0	0	0
T15	0	358	0	0
T16	0	414	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T44	1757	0	0	0
T51	0	1107	0	0
T56	0	592	0	0
T62	2212	0	0	0
T63	1771	0	0	0
T99	0	1020	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	137425	0	0
T4	2259	656	0	0
T5	2861	0	0	0
T6	0	211	0	0
T7	0	211	0	0
T8	0	731	0	0
T9	0	607	0	0
T11	2459	0	0	0
T15	0	359	0	0
T16	0	415	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	0	0	0
T28	1667	0	0	0
T44	1757	0	0	0
T51	0	1108	0	0
T56	0	593	0	0
T62	2212	0	0	0
T63	1771	0	0	0
T99	0	1021	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207139068	206964491	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	1046	867	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0