Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T30,T33
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T34,T35
1	0	1	Covered	T3,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	413698574	660335	0	0
DepthKnown_A	414352430	414003276	0	0
RvalidKnown_A	414352430	414003276	0	0
WreadyKnown_A	414352430	414003276	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	414051782	747996	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	413698574	660335	0	0
T3	5290	2399	0	0
T4	314	0	0	0
T5	5722	0	0	0
T7	0	93	0	0
T8	0	53	0	0
T9	0	255	0	0
T10	6010	3075	0	0
T11	4918	2216	0	0
T16	0	237	0	0
T20	0	10400	0	0
T22	2880	0	0	0
T23	1900	0	0	0
T24	6238	0	0	0
T27	3276	331	0	0
T44	3514	0	0	0
T90	0	612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414352430	414003276	0	0
T1	7910	7712	0	0
T2	4754	4590	0	0
T3	5290	5124	0	0
T4	4518	4160	0	0
T5	5722	5406	0	0
T10	6010	5880	0	0
T11	4918	4788	0	0
T22	2880	2706	0	0
T23	1900	1704	0	0
T24	6238	6044	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414352430	414003276	0	0
T1	7910	7712	0	0
T2	4754	4590	0	0
T3	5290	5124	0	0
T4	4518	4160	0	0
T5	5722	5406	0	0
T10	6010	5880	0	0
T11	4918	4788	0	0
T22	2880	2706	0	0
T23	1900	1704	0	0
T24	6238	6044	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414352430	414003276	0	0
T1	7910	7712	0	0
T2	4754	4590	0	0
T3	5290	5124	0	0
T4	4518	4160	0	0
T5	5722	5406	0	0
T10	6010	5880	0	0
T11	4918	4788	0	0
T22	2880	2706	0	0
T23	1900	1704	0	0
T24	6238	6044	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	414051782	747996	0	0
T3	5290	2399	0	0
T4	4518	2269	0	0
T5	5722	0	0	0
T6	0	312	0	0
T7	0	520	0	0
T8	0	1122	0	0
T10	6010	3075	0	0
T11	4918	2216	0	0
T20	0	10400	0	0
T22	2880	0	0	0
T23	1900	0	0	0
T24	6238	0	0	0
T27	3276	331	0	0
T44	3514	0	0	0
T90	0	612	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T94,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T30,T95
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T29,T96,T97
1	0	1	Covered	T3,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206849287	323519	0	0
DepthKnown_A	207176215	207001638	0	0
RvalidKnown_A	207176215	207001638	0	0
WreadyKnown_A	207176215	207001638	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207025891	367102	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206849287	323519	0	0
T3	2645	1179	0	0
T4	157	0	0	0
T5	2861	0	0	0
T7	0	45	0	0
T8	0	21	0	0
T9	0	107	0	0
T10	3005	1501	0	0
T11	2459	1075	0	0
T16	0	71	0	0
T20	0	5171	0	0
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	167	0	0
T44	1757	0	0	0
T90	0	309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207025891	367102	0	0
T3	2645	1179	0	0
T4	2259	1141	0	0
T5	2861	0	0	0
T6	0	157	0	0
T7	0	253	0	0
T8	0	608	0	0
T10	3005	1501	0	0
T11	2459	1075	0	0
T20	0	5171	0	0
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	167	0	0
T44	1757	0	0	0
T90	0	309	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T33
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T98
1	0	1	Covered	T3,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	206849287	336816	0	0
DepthKnown_A	207176215	207001638	0	0
RvalidKnown_A	207176215	207001638	0	0
WreadyKnown_A	207176215	207001638	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207025891	380894	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206849287	336816	0	0
T3	2645	1220	0	0
T4	157	0	0	0
T5	2861	0	0	0
T7	0	48	0	0
T8	0	32	0	0
T9	0	148	0	0
T10	3005	1574	0	0
T11	2459	1141	0	0
T16	0	166	0	0
T20	0	5229	0	0
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	164	0	0
T44	1757	0	0	0
T90	0	303	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207176215	207001638	0	0
T1	3955	3856	0	0
T2	2377	2295	0	0
T3	2645	2562	0	0
T4	2259	2080	0	0
T5	2861	2703	0	0
T10	3005	2940	0	0
T11	2459	2394	0	0
T22	1440	1353	0	0
T23	950	852	0	0
T24	3119	3022	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207025891	380894	0	0
T3	2645	1220	0	0
T4	2259	1128	0	0
T5	2861	0	0	0
T6	0	155	0	0
T7	0	267	0	0
T8	0	514	0	0
T10	3005	1574	0	0
T11	2459	1141	0	0
T20	0	5229	0	0
T22	1440	0	0	0
T23	950	0	0	0
T24	3119	0	0	0
T27	1638	164	0	0
T44	1757	0	0	0
T90	0	303	0	0