Group : tb.dut.u_edn_cov_if::edn_alert_cg
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Group : tb.dut.u_edn_cov_if::edn_alert_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
83.33 83.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_alert_cg 83.33 1 100 1 64 64




Group Instance : edn_alert_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance edn_alert_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance edn_alert_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_recov_alert_cg 6 1 5 83.33 100 1 1 0


Summary for Variable cp_recov_alert_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 1 5 83.33


Automatically Generated Bins for cp_recov_alert_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[csrng_ack_err] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[edn_enable_field_alert] 57 1 T27 1 T39 1 T55 1
auto[boot_req_mode_field_alert] 48 1 T47 1 T90 1 T91 1
auto[auto_req_mode_field_alert] 58 1 T2 1 T45 1 T88 1
auto[cmd_fifo_rst_field_alert] 37 1 T28 1 T69 1 T92 1
auto[edn_bus_cmp_alert] 200 1 T2 1 T27 1 T28 1

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