Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	676639	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5484584

1

T1

39

T2

25

T3

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1625545	1			T1	339		T2	27		T3	29
values[0x0]	2097835	1			T1	20		T2	15		T3	12
values[0x1]	2437843	1			T1	16		T2	10		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5827191

1

T1

156

T2

32

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22668	1			T1	1		T4	1		T5	206
valid_sources[0x01]	24347	1			T1	1		T3	2		T5	194
valid_sources[0x02]	24540	1			T1	2		T2	5		T5	226
valid_sources[0x03]	25738	1			T1	1		T5	204		T35	371
valid_sources[0x04]	23214	1			T1	1		T3	1		T4	1
valid_sources[0x05]	23957	1			T1	2		T5	226		T15	1
valid_sources[0x06]	22810	1			T1	2		T5	201		T35	368
valid_sources[0x07]	22870	1			T4	2		T5	212		T35	384
valid_sources[0x08]	23680	1			T1	1		T3	1		T5	198
valid_sources[0x09]	25387	1			T5	188		T9	4		T35	421
valid_sources[0x0a]	24056	1			T1	2		T5	197		T35	388
valid_sources[0x0b]	23902	1			T1	1		T2	1		T5	193
valid_sources[0x0c]	23928	1			T1	1		T3	1		T5	188
valid_sources[0x0d]	22154	1			T1	1		T4	2		T5	200
valid_sources[0x0e]	25967	1			T5	175		T35	403		T60	1
valid_sources[0x0f]	23017	1			T1	1		T5	187		T27	1
valid_sources[0x10]	23029	1			T1	1		T5	217		T14	2
valid_sources[0x11]	24598	1			T1	2		T3	1		T5	184
valid_sources[0x12]	24126	1			T5	203		T15	1		T35	369
valid_sources[0x13]	23656	1			T5	193		T27	1		T35	438
valid_sources[0x14]	23141	1			T1	2		T5	183		T35	403
valid_sources[0x15]	24353	1			T5	208		T35	391		T60	10
valid_sources[0x16]	23416	1			T5	191		T27	2		T35	420
valid_sources[0x17]	24352	1			T3	1		T4	2		T5	185
valid_sources[0x18]	23119	1			T1	4		T5	180		T27	1
valid_sources[0x19]	23712	1			T1	1		T5	178		T14	1
valid_sources[0x1a]	22946	1			T5	197		T35	365		T60	5
valid_sources[0x1b]	23600	1			T1	1		T3	1		T5	195
valid_sources[0x1c]	23487	1			T5	207		T35	346		T60	7
valid_sources[0x1d]	23732	1			T1	1		T5	199		T27	1
valid_sources[0x1e]	24772	1			T1	4		T5	206		T14	2
valid_sources[0x1f]	21784	1			T1	1		T5	221		T27	3
valid_sources[0x20]	24617	1			T1	4		T5	193		T35	382
valid_sources[0x21]	24443	1			T5	192		T35	433		T28	1
valid_sources[0x22]	24291	1			T5	155		T35	381		T60	10
valid_sources[0x23]	26081	1			T1	2		T3	1		T5	223
valid_sources[0x24]	25575	1			T1	1		T5	175		T27	2
valid_sources[0x25]	23185	1			T5	165		T9	1		T35	367
valid_sources[0x26]	24743	1			T1	1		T4	1		T5	183
valid_sources[0x27]	22593	1			T1	1		T5	176		T35	353
valid_sources[0x28]	23639	1			T1	3		T5	223		T14	1
valid_sources[0x29]	22558	1			T1	2		T3	1		T5	180
valid_sources[0x2a]	22802	1			T1	1		T5	201		T35	366
valid_sources[0x2b]	22835	1			T1	1		T3	1		T4	1
valid_sources[0x2c]	23000	1			T1	3		T5	190		T7	1
valid_sources[0x2d]	24907	1			T1	2		T5	162		T35	422
valid_sources[0x2e]	25976	1			T1	1		T4	1		T5	216
valid_sources[0x2f]	25292	1			T1	1		T3	1		T5	188
valid_sources[0x30]	25234	1			T1	1		T2	2		T5	201
valid_sources[0x31]	23272	1			T1	1		T4	1		T5	180
valid_sources[0x32]	24237	1			T1	4		T5	194		T35	404
valid_sources[0x33]	24394	1			T1	2		T3	2		T5	193
valid_sources[0x34]	24809	1			T1	5		T3	1		T5	182
valid_sources[0x35]	23743	1			T1	1		T5	209		T27	5
valid_sources[0x36]	23497	1			T1	1		T5	243		T35	399
valid_sources[0x37]	23982	1			T1	1		T5	180		T35	354
valid_sources[0x38]	26662	1			T1	8		T4	2		T5	185
valid_sources[0x39]	23575	1			T1	1		T5	208		T7	1
valid_sources[0x3a]	24523	1			T1	1		T5	184		T35	362
valid_sources[0x3b]	22898	1			T1	2		T5	167		T9	1
valid_sources[0x3c]	22140	1			T1	1		T3	1		T5	175
valid_sources[0x3d]	22981	1			T1	2		T3	1		T5	203
valid_sources[0x3e]	25005	1			T1	2		T2	1		T5	158
valid_sources[0x3f]	25095	1			T1	2		T5	167		T35	397
valid_sources[0x40]	24056	1			T1	2		T5	183		T35	409
valid_sources[0x41]	23768	1			T5	220		T35	414		T13	1
valid_sources[0x42]	23160	1			T1	1		T5	195		T7	1
valid_sources[0x43]	26545	1			T1	3		T4	2		T5	177
valid_sources[0x44]	23878	1			T1	2		T5	194		T35	373
valid_sources[0x45]	24724	1			T2	1		T5	186		T35	384
valid_sources[0x46]	22776	1			T5	152		T35	361		T60	6
valid_sources[0x47]	25071	1			T4	1		T5	196		T7	9
valid_sources[0x48]	24861	1			T1	1		T5	158		T35	410
valid_sources[0x49]	22747	1			T1	1		T5	181		T35	373
valid_sources[0x4a]	24316	1			T1	4		T4	1		T5	211
valid_sources[0x4b]	22994	1			T5	161		T9	1		T35	421
valid_sources[0x4c]	23745	1			T1	4		T2	1		T5	155
valid_sources[0x4d]	23929	1			T1	4		T5	185		T7	3
valid_sources[0x4e]	23730	1			T1	2		T2	6		T5	191
valid_sources[0x4f]	23561	1			T4	1		T5	223		T35	416
valid_sources[0x50]	24714	1			T1	1		T5	144		T9	2
valid_sources[0x51]	23946	1			T1	1		T3	1		T5	201
valid_sources[0x52]	25654	1			T1	4		T5	182		T35	374
valid_sources[0x53]	24194	1			T2	1		T5	179		T27	1
valid_sources[0x54]	23050	1			T5	181		T9	2		T35	438
valid_sources[0x55]	22769	1			T1	3		T5	177		T9	2
valid_sources[0x56]	22394	1			T1	1		T5	199		T14	1
valid_sources[0x57]	23119	1			T1	2		T5	187		T27	1
valid_sources[0x58]	24339	1			T4	1		T5	184		T7	3
valid_sources[0x59]	25049	1			T3	1		T5	171		T35	349
valid_sources[0x5a]	25742	1			T1	3		T5	208		T35	378
valid_sources[0x5b]	23677	1			T1	3		T4	1		T5	163
valid_sources[0x5c]	23247	1			T1	1		T3	1		T4	2
valid_sources[0x5d]	24714	1			T1	3		T5	225		T35	411
valid_sources[0x5e]	24068	1			T1	5		T5	167		T9	2
valid_sources[0x5f]	24060	1			T1	1		T5	186		T7	2
valid_sources[0x60]	24639	1			T2	3		T5	184		T9	1
valid_sources[0x61]	23639	1			T5	205		T35	411		T60	9
valid_sources[0x62]	24794	1			T2	5		T4	1		T5	193
valid_sources[0x63]	23249	1			T1	1		T5	200		T35	419
valid_sources[0x64]	24305	1			T1	2		T4	1		T5	180
valid_sources[0x65]	24029	1			T1	3		T5	239		T7	1
valid_sources[0x66]	22790	1			T1	2		T5	185		T35	415
valid_sources[0x67]	22506	1			T1	3		T5	188		T7	1
valid_sources[0x68]	23628	1			T5	156		T35	406		T60	3
valid_sources[0x69]	24376	1			T1	2		T4	1		T5	209
valid_sources[0x6a]	23021	1			T1	1		T3	1		T5	180
valid_sources[0x6b]	23704	1			T1	3		T5	205		T27	2
valid_sources[0x6c]	24256	1			T1	2		T5	164		T7	3
valid_sources[0x6d]	25478	1			T1	1		T5	195		T9	2
valid_sources[0x6e]	23527	1			T1	2		T5	208		T35	402
valid_sources[0x6f]	24666	1			T1	4		T5	193		T35	385
valid_sources[0x70]	23484	1			T1	2		T5	210		T27	2
valid_sources[0x71]	26755	1			T1	1		T4	3		T5	189
valid_sources[0x72]	24395	1			T4	3		T5	175		T35	397
valid_sources[0x73]	24197	1			T1	1		T5	189		T35	402
valid_sources[0x74]	25217	1			T1	1		T3	1		T5	194
valid_sources[0x75]	25663	1			T5	203		T7	1		T35	401
valid_sources[0x76]	22526	1			T1	1		T5	194		T9	3
valid_sources[0x77]	23663	1			T1	2		T3	1		T4	1
valid_sources[0x78]	24458	1			T5	172		T35	339		T60	12
valid_sources[0x79]	24833	1			T1	1		T5	162		T35	397
valid_sources[0x7a]	24235	1			T1	4		T4	1		T5	182
valid_sources[0x7b]	23252	1			T1	1		T5	198		T7	1
valid_sources[0x7c]	23496	1			T5	187		T15	1		T35	423
valid_sources[0x7d]	22545	1			T5	199		T35	373		T60	1
valid_sources[0x7e]	24893	1			T5	220		T7	3		T35	357
valid_sources[0x7f]	26013	1			T4	2		T5	211		T35	385
valid_sources[0x80]	24694	1			T1	5		T5	185		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1381090

1

T1

7

T2

11

T3

9

values[0x0]

all_enables

biggest_size

2054737

1

T1

19

T2

10

T3

7

values[0x1]

all_enables

biggest_size

2048757

1

T1

13

T2

4

T3

2