Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2777	1			T1	1		T5	29		T23	2
non_zero_bins[1]	1967	1			T1	2		T5	18		T23	1
zero	9269	1			T1	1		T2	6		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	524	1			T5	6		T35	9		T60	3
uni	3690	1			T1	1		T3	1		T5	37
gen	4482	1			T1	1		T2	3		T3	1
res	874	1			T1	1		T5	5		T9	2
ins	4443	1			T1	1		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9220

1

T1

2

T2

1

T3

3

mubi_true

4793

1

T1

2

T2

5

T5

41

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

21

1

T55

1

T267

1

T268

1

pass

13992

1

T1

4

T2

6

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	125	1			T5	3		T35	3		T60	1
upd	non_zero_bins[0]	pass	mubi_true	145	1			T5	2		T35	2		T60	2
upd	non_zero_bins[1]	pass	mubi_false	83	1			T36	1		T86	1		T212	3
upd	non_zero_bins[1]	pass	mubi_true	71	1			T35	1		T86	2		T212	2
upd	zero	pass	mubi_false	51	1			T35	1		T36	1		T86	1
upd	zero	pass	mubi_true	49	1			T5	1		T35	2		T36	2
uni	zero	pass	mubi_false	2738	1			T1	1		T3	1		T5	25
uni	zero	pass	mubi_true	952	1			T5	12		T35	10		T60	5
gen	non_zero_bins[0]	pass	mubi_false	485	1			T5	3		T23	1		T9	1
gen	non_zero_bins[0]	pass	mubi_true	517	1			T5	6		T35	7		T60	2
gen	non_zero_bins[1]	pass	mubi_false	387	1			T5	1		T9	3		T35	4
gen	non_zero_bins[1]	pass	mubi_true	405	1			T1	1		T5	3		T35	7
gen	zero	fail	mubi_false	19	1			T267	1		T268	1		T269	1
gen	zero	pass	mubi_false	1933	1			T2	1		T3	1		T4	1
gen	zero	pass	mubi_true	736	1			T2	2		T5	2		T23	1
res	non_zero_bins[0]	pass	mubi_false	176	1			T1	1		T35	4		T13	2
res	non_zero_bins[0]	pass	mubi_true	202	1			T35	2		T21	2		T36	2
res	non_zero_bins[1]	pass	mubi_false	145	1			T5	1		T35	1		T63	1
res	non_zero_bins[1]	pass	mubi_true	152	1			T5	3		T9	2		T35	2
res	zero	fail	mubi_false	2	1			T55	1		T143	1		-	-
res	zero	pass	mubi_false	108	1			T5	1		T63	1		T36	1
res	zero	pass	mubi_true	89	1			T36	1		T270	2		T212	1
ins	non_zero_bins[0]	pass	mubi_false	547	1			T5	7		T23	1		T35	6
ins	non_zero_bins[0]	pass	mubi_true	580	1			T5	8		T35	13		T60	1
ins	non_zero_bins[1]	pass	mubi_false	372	1			T5	6		T35	7		T13	1
ins	non_zero_bins[1]	pass	mubi_true	352	1			T1	1		T5	4		T23	1
ins	zero	pass	mubi_false	2049	1			T3	1		T4	1		T5	13
ins	zero	pass	mubi_true	543	1			T2	3		T23	1		T15	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded