Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T15,T27
1	1	Covered	T2,T23,T14

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T39
1	1	Covered	T6,T7,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T27,T28
1	0	Covered	T4,T6,T7

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T4,T6,T7

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T4,T6,T7

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T13,T21
AutoCaptGenCnt	143	Covered	T6,T9,T13
AutoCaptReseedCnt	141	Covered	T9,T13,T21
AutoDispatch	125	Covered	T6,T9,T13
AutoFirstAckWait	119	Covered	T6,T9,T13
AutoLoadIns	69	Covered	T6,T7,T9
AutoSendGenCmd	150	Covered	T6,T9,T13
AutoSendReseedCmd	162	Covered	T9,T13,T21
BootDone	98	Covered	T2,T23,T14
BootGenAckWait	90	Covered	T2,T23,T14
BootInsAckWait	80	Covered	T2,T23,T14
BootLoadGen	85	Covered	T2,T23,T14
BootLoadIns	65	Covered	T2,T23,T14
BootLoadUni	102	Covered	T2,T23,T28
BootPulse	94	Covered	T2,T23,T14
BootUniAckWait	107	Covered	T2,T23,T28
Error	188	Covered	T4,T6,T7
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T2,T27,T28
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T9,T13,T21
AutoAckWait->Error	188	Covered	T59,T103,T104
AutoAckWait->Idle	211	Covered	T20,T40,T41
AutoAckWait->RejectCsrngEntropy	188	Covered	T76,T90,T105
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T6,T9,T13
AutoCaptGenCnt->Error	188	Covered	T106,T107,T108
AutoCaptGenCnt->Idle	211	Covered	T20,T40,T72
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T109,T69,T91
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T9,T13,T21
AutoCaptReseedCnt->Error	188	Covered	T110,T111,T112
AutoCaptReseedCnt->Idle	211	Covered	T113,T114,T115
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T116,T117,T118
AutoDispatch->AutoCaptGenCnt	143	Covered	T6,T9,T13
AutoDispatch->AutoCaptReseedCnt	141	Covered	T9,T13,T21
AutoDispatch->Error	188	Covered	T8,T119,T120
AutoDispatch->Idle	138	Covered	T9,T13,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T88,T121,T122
AutoFirstAckWait->AutoDispatch	125	Covered	T6,T9,T13
AutoFirstAckWait->Error	188	Covered	T123
AutoFirstAckWait->Idle	211	Covered	T124,T125,T126
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T67,T127,T128
AutoLoadIns->AutoFirstAckWait	119	Covered	T6,T9,T13
AutoLoadIns->Error	188	Covered	T7,T57,T129
AutoLoadIns->Idle	211	Covered	T6,T7,T8
AutoLoadIns->RejectCsrngEntropy	188	Covered	T28,T130,T131
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T13,T21
AutoSendGenCmd->Error	188	Covered	T6,T132,T133
AutoSendGenCmd->Idle	211	Covered	T134,T135,T136
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T137,T138,T139
AutoSendReseedCmd->AutoAckWait	168	Covered	T9,T13,T21
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T140,T141,T142
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T55,T95,T143
BootDone->BootLoadUni	102	Covered	T2,T23,T28
BootDone->Error	188	Covered	T58,T144,T145
BootDone->Idle	211	Covered	T52,T58,T146
BootDone->RejectCsrngEntropy	188	Covered	T147,T148,T149
BootGenAckWait->BootPulse	94	Covered	T2,T23,T14
BootGenAckWait->Error	188	Covered	T150
BootGenAckWait->Idle	211	Covered	T151,T56,T73
BootGenAckWait->RejectCsrngEntropy	188	Covered	T152,T153,T98
BootInsAckWait->BootLoadGen	85	Covered	T2,T23,T14
BootInsAckWait->Error	188	Covered	T151,T56,T154
BootInsAckWait->Idle	211	Covered	T14,T15,T68
BootInsAckWait->RejectCsrngEntropy	188	Covered	T2,T39,T97
BootLoadGen->BootGenAckWait	90	Covered	T2,T23,T14
BootLoadGen->Error	188	Covered	T155,T156
BootLoadGen->Idle	211	Covered	T48,T157,T158
BootLoadGen->RejectCsrngEntropy	188	Covered	T27,T47,T92
BootLoadIns->BootInsAckWait	80	Covered	T2,T23,T14
BootLoadIns->Error	188	Covered	T15,T159,T160
BootLoadIns->Idle	211	Covered	T161,T162,T163
BootLoadIns->RejectCsrngEntropy	188	Covered	T164,T165,T166
BootLoadUni->BootUniAckWait	107	Covered	T2,T23,T28
BootLoadUni->Error	188	Covered	T68,T167,T168
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T169,T170,T171
BootPulse->BootDone	98	Covered	T2,T23,T14
BootPulse->Error	188	Covered	T14,T172,T173
BootPulse->Idle	211	Covered	T78,T174,T175
BootPulse->RejectCsrngEntropy	188	Covered	T49,T176,T177
BootUniAckWait->Error	188	Covered	T178,T179,T180
BootUniAckWait->Idle	112	Covered	T2,T23,T28
BootUniAckWait->RejectCsrngEntropy	188	Covered	T45,T181,T182
Idle->AutoLoadIns	69	Covered	T6,T7,T9
Idle->BootLoadIns	65	Covered	T2,T23,T14
Idle->Error	188	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T2,T27,T28
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T183,T184,T185
RejectCsrngEntropy->Idle	211	Covered	T2,T27,T28
SWPortMode->Error	188	Covered	T4,T16,T38
SWPortMode->Idle	211	Covered	T3,T5,T27
SWPortMode->RejectCsrngEntropy	188	Covered	T39,T76,T109

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T14
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T23,T28
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T14,T15
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T23,T28
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T23,T45,T37
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T23,T28
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T9,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T6,T7,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T9,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T13,T21
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T13,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T13,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T9,T13,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T6,T9,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T6,T9,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T13,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T13,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T9,T13,T21
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T75,T83

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T6,T7
1	0	1	-	Not Covered
1	0	0	-	Covered	T2,T27,T28
0	-	-	1	Covered	T2,T6,T7
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	217284529	169154	0	0
FpvSecCmErrorStEscalate_A	217284529	170455	0	0
u_state_regs_A	217248751	217048908	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	169154	0	0
T4	741	308	0	0
T5	190600	0	0	0
T6	2418	1122	0	0
T7	631	262	0	0
T8	0	1102	0	0
T9	5599	0	0	0
T14	1813	1042	0	0
T15	795	406	0	0
T16	24709	8982	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T38	0	360	0	0
T68	0	1110	0	0
T151	0	1123	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	170455	0	0
T4	741	309	0	0
T5	190600	0	0	0
T6	2418	1123	0	0
T7	631	263	0	0
T8	0	1103	0	0
T9	5599	0	0	0
T14	1813	1043	0	0
T15	795	407	0	0
T16	24709	9112	0	0
T23	2398	0	0	0
T27	1969	0	0	0
T38	0	361	0	0
T68	0	1111	0	0
T151	0	1124	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217248751	217048908	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	629	479	0	0
T5	190600	190591	0	0
T6	2076	1882	0	0
T7	505	371	0	0
T14	1646	1501	0	0
T15	605	459	0	0
T23	2398	2333	0	0