Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T31,T32
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T33,T34
1	0	1	Covered	T6,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T6,T9,T13

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	433769572	1113423	0	0
DepthKnown_A	434569058	434169372	0	0
RvalidKnown_A	434569058	434169372	0	0
WreadyKnown_A	434569058	434169372	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	434156014	1197101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433769572	1113423	0	0
T6	682	334	0	0
T7	248	55	0	0
T8	0	71	0	0
T9	11198	7098	0	0
T13	0	2062	0	0
T14	280	0	0	0
T15	310	0	0	0
T16	1432	0	0	0
T19	0	2241	0	0
T21	0	1210	0	0
T27	3938	0	0	0
T28	4494	366	0	0
T35	564096	0	0	0
T39	0	95	0	0
T45	4846	0	0	0
T55	0	430	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434569058	434169372	0	0
T1	4262	4122	0	0
T2	3702	3528	0	0
T3	5628	5338	0	0
T4	1482	1182	0	0
T5	381200	381182	0	0
T6	4836	4448	0	0
T7	1262	994	0	0
T14	3626	3336	0	0
T15	1590	1298	0	0
T23	4796	4666	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434569058	434169372	0	0
T1	4262	4122	0	0
T2	3702	3528	0	0
T3	5628	5338	0	0
T4	1482	1182	0	0
T5	381200	381182	0	0
T6	4836	4448	0	0
T7	1262	994	0	0
T14	3626	3336	0	0
T15	1590	1298	0	0
T23	4796	4666	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434569058	434169372	0	0
T1	4262	4122	0	0
T2	3702	3528	0	0
T3	5628	5338	0	0
T4	1482	1182	0	0
T5	381200	381182	0	0
T6	4836	4448	0	0
T7	1262	994	0	0
T14	3626	3336	0	0
T15	1590	1298	0	0
T23	4796	4666	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	434156014	1197101	0	0
T6	4836	1957	0	0
T7	1262	522	0	0
T9	11198	7098	0	0
T13	0	2062	0	0
T14	3626	310	0	0
T15	1590	268	0	0
T16	1432	0	0	0
T19	0	2241	0	0
T21	0	1210	0	0
T27	3938	0	0	0
T28	4494	366	0	0
T35	564096	0	0	0
T39	0	95	0	0
T45	4846	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30
1	0	1	Covered	T6,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T6,T9,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216884786	562189	0	0
DepthKnown_A	217284529	217084686	0	0
RvalidKnown_A	217284529	217084686	0	0
WreadyKnown_A	217284529	217084686	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217078007	604106	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216884786	562189	0	0
T6	341	214	0	0
T7	124	30	0	0
T8	0	48	0	0
T9	5599	3565	0	0
T13	0	1056	0	0
T14	140	0	0	0
T15	155	0	0	0
T16	716	0	0	0
T19	0	1135	0	0
T21	0	641	0	0
T27	1969	0	0	0
T28	2247	176	0	0
T35	282048	0	0	0
T39	0	52	0	0
T45	2423	0	0	0
T55	0	293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217078007	604106	0	0
T6	2418	995	0	0
T7	631	267	0	0
T9	5599	3565	0	0
T13	0	1056	0	0
T14	1813	154	0	0
T15	795	133	0	0
T16	716	0	0	0
T19	0	1135	0	0
T21	0	641	0	0
T27	1969	0	0	0
T28	2247	176	0	0
T35	282048	0	0	0
T39	0	52	0	0
T45	2423	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T40,T29,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T31,T32
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T34
1	0	1	Covered	T6,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T9,T13,T21

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	216884786	551234	0	0
DepthKnown_A	217284529	217084686	0	0
RvalidKnown_A	217284529	217084686	0	0
WreadyKnown_A	217284529	217084686	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	217078007	592995	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216884786	551234	0	0
T6	341	120	0	0
T7	124	25	0	0
T8	0	23	0	0
T9	5599	3533	0	0
T13	0	1006	0	0
T14	140	0	0	0
T15	155	0	0	0
T16	716	0	0	0
T19	0	1106	0	0
T21	0	569	0	0
T27	1969	0	0	0
T28	2247	190	0	0
T35	282048	0	0	0
T39	0	43	0	0
T45	2423	0	0	0
T55	0	137	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217284529	217084686	0	0
T1	2131	2061	0	0
T2	1851	1764	0	0
T3	2814	2669	0	0
T4	741	591	0	0
T5	190600	190591	0	0
T6	2418	2224	0	0
T7	631	497	0	0
T14	1813	1668	0	0
T15	795	649	0	0
T23	2398	2333	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	217078007	592995	0	0
T6	2418	962	0	0
T7	631	255	0	0
T9	5599	3533	0	0
T13	0	1006	0	0
T14	1813	156	0	0
T15	795	135	0	0
T16	716	0	0	0
T19	0	1106	0	0
T21	0	569	0	0
T27	1969	0	0	0
T28	2247	190	0	0
T35	282048	0	0	0
T39	0	43	0	0
T45	2423	0	0	0