Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679347	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5554726

1

T1

43

T2

64

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1641611	1			T1	215		T2	75		T3	89
values[0x0]	2124091	1			T1	22		T2	34		T3	9
values[0x1]	2468371	1			T1	21		T2	32		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5899274

1

T1

110

T2

89

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24805	1			T4	533		T28	1		T32	1
valid_sources[0x01]	25503	1			T4	753		T28	1		T10	2
valid_sources[0x02]	25052	1			T18	1		T4	595		T24	4
valid_sources[0x03]	23671	1			T18	2		T19	1		T27	2
valid_sources[0x04]	21698	1			T18	2		T4	379		T53	26
valid_sources[0x05]	25497	1			T27	1		T4	623		T25	34
valid_sources[0x06]	23753	1			T4	460		T28	2		T42	1
valid_sources[0x07]	24767	1			T27	1		T23	2		T4	952
valid_sources[0x08]	24765	1			T4	335		T10	1		T44	1
valid_sources[0x09]	24530	1			T19	2		T4	786		T5	3
valid_sources[0x0a]	25214	1			T4	480		T32	1		T10	1
valid_sources[0x0b]	23311	1			T4	171		T10	1		T60	1
valid_sources[0x0c]	26231	1			T27	1		T4	336		T10	1
valid_sources[0x0d]	24946	1			T4	867		T42	3		T52	14
valid_sources[0x0e]	23668	1			T19	7		T4	693		T49	1
valid_sources[0x0f]	24477	1			T27	1		T4	483		T61	1
valid_sources[0x10]	23107	1			T18	3		T27	1		T4	655
valid_sources[0x11]	23564	1			T4	696		T10	1		T44	2
valid_sources[0x12]	25675	1			T4	1063		T28	1		T42	1
valid_sources[0x13]	22785	1			T4	1151		T52	2		T40	712
valid_sources[0x14]	23512	1			T18	1		T19	1		T4	809
valid_sources[0x15]	25198	1			T4	211		T42	2		T44	1
valid_sources[0x16]	23470	1			T18	1		T23	2		T4	435
valid_sources[0x17]	24775	1			T18	2		T4	614		T42	2
valid_sources[0x18]	25993	1			T4	769		T10	3		T44	3
valid_sources[0x19]	24082	1			T4	1212		T15	1		T61	3
valid_sources[0x1a]	24822	1			T4	777		T6	1		T42	1
valid_sources[0x1b]	24084	1			T27	1		T4	603		T44	3
valid_sources[0x1c]	24590	1			T4	678		T32	1		T10	3
valid_sources[0x1d]	24466	1			T23	2		T4	816		T42	1
valid_sources[0x1e]	24811	1			T4	386		T40	788		T41	255
valid_sources[0x1f]	25003	1			T27	1		T4	1117		T32	1
valid_sources[0x20]	23347	1			T18	2		T23	2		T4	322
valid_sources[0x21]	25582	1			T4	701		T10	3		T15	1
valid_sources[0x22]	24299	1			T4	188		T44	1		T52	4
valid_sources[0x23]	24661	1			T4	471		T44	2		T52	2
valid_sources[0x24]	23733	1			T4	541		T15	1		T42	1
valid_sources[0x25]	25158	1			T18	1		T4	663		T10	3
valid_sources[0x26]	23297	1			T4	530		T60	2		T73	2
valid_sources[0x27]	24392	1			T18	2		T4	470		T32	1
valid_sources[0x28]	24705	1			T18	1		T23	2		T4	390
valid_sources[0x29]	22659	1			T19	4		T4	177		T32	2
valid_sources[0x2a]	26038	1			T4	1200		T73	1		T40	777
valid_sources[0x2b]	24053	1			T23	1		T4	1401		T28	1
valid_sources[0x2c]	24569	1			T4	482		T50	2		T40	677
valid_sources[0x2d]	23668	1			T18	1		T4	151		T76	1
valid_sources[0x2e]	22564	1			T4	298		T10	1		T42	1
valid_sources[0x2f]	23990	1			T4	818		T10	1		T42	1
valid_sources[0x30]	24357	1			T4	389		T10	1		T52	7
valid_sources[0x31]	23513	1			T19	1		T23	1		T4	422
valid_sources[0x32]	23002	1			T18	1		T23	2		T4	495
valid_sources[0x33]	24803	1			T18	2		T27	1		T4	989
valid_sources[0x34]	25159	1			T4	1184		T52	6		T40	766
valid_sources[0x35]	23936	1			T4	265		T42	1		T40	665
valid_sources[0x36]	25772	1			T18	1		T4	1010		T28	1
valid_sources[0x37]	24334	1			T19	5		T27	1		T4	440
valid_sources[0x38]	24319	1			T4	980		T51	4		T40	648
valid_sources[0x39]	23942	1			T4	1217		T10	1		T40	612
valid_sources[0x3a]	23230	1			T4	248		T6	1		T50	1
valid_sources[0x3b]	22909	1			T18	1		T19	1		T4	601
valid_sources[0x3c]	25288	1			T4	715		T32	1		T44	1
valid_sources[0x3d]	23835	1			T4	701		T42	1		T44	3
valid_sources[0x3e]	22675	1			T27	2		T4	294		T52	4
valid_sources[0x3f]	24111	1			T19	4		T4	347		T10	1
valid_sources[0x40]	24715	1			T4	700		T32	1		T42	1
valid_sources[0x41]	23115	1			T4	426		T32	1		T40	728
valid_sources[0x42]	25902	1			T4	795		T28	2		T42	2
valid_sources[0x43]	22331	1			T18	2		T4	39		T42	2
valid_sources[0x44]	25086	1			T4	716		T42	3		T44	1
valid_sources[0x45]	24024	1			T19	1		T4	236		T15	1
valid_sources[0x46]	24134	1			T19	3		T4	607		T61	4
valid_sources[0x47]	26445	1			T4	561		T10	5		T15	1
valid_sources[0x48]	24725	1			T4	808		T6	1		T25	1
valid_sources[0x49]	23562	1			T18	1		T4	715		T42	1
valid_sources[0x4a]	24693	1			T4	865		T61	11		T50	1
valid_sources[0x4b]	25434	1			T19	1		T4	479		T28	1
valid_sources[0x4c]	24608	1			T4	620		T5	2		T40	801
valid_sources[0x4d]	24595	1			T19	3		T4	651		T42	1
valid_sources[0x4e]	23438	1			T4	545		T60	1		T40	646
valid_sources[0x4f]	24728	1			T27	1		T4	382		T10	1
valid_sources[0x50]	25261	1			T4	892		T5	2		T10	2
valid_sources[0x51]	26201	1			T18	3		T4	710		T44	1
valid_sources[0x52]	24644	1			T27	1		T4	593		T28	1
valid_sources[0x53]	23641	1			T4	506		T32	2		T10	3
valid_sources[0x54]	23913	1			T4	814		T42	1		T76	1
valid_sources[0x55]	24043	1			T18	2		T4	673		T52	1
valid_sources[0x56]	24546	1			T4	310		T6	3		T60	2
valid_sources[0x57]	24038	1			T27	1		T4	778		T42	1
valid_sources[0x58]	22814	1			T18	1		T19	1		T4	365
valid_sources[0x59]	25019	1			T18	1		T23	3		T4	622
valid_sources[0x5a]	22937	1			T19	3		T23	42		T4	98
valid_sources[0x5b]	24862	1			T18	2		T4	753		T28	1
valid_sources[0x5c]	24528	1			T4	824		T6	3		T42	1
valid_sources[0x5d]	23872	1			T4	1013		T42	1		T44	1
valid_sources[0x5e]	24376	1			T4	561		T32	1		T10	1
valid_sources[0x5f]	25461	1			T23	1		T4	634		T28	1
valid_sources[0x60]	23422	1			T4	270		T32	1		T10	2
valid_sources[0x61]	22569	1			T27	1		T4	397		T32	1
valid_sources[0x62]	23378	1			T18	1		T4	769		T10	2
valid_sources[0x63]	25321	1			T18	1		T23	1		T4	486
valid_sources[0x64]	23063	1			T4	540		T10	1		T52	2
valid_sources[0x65]	24578	1			T4	450		T10	2		T42	1
valid_sources[0x66]	23249	1			T4	494		T10	2		T42	1
valid_sources[0x67]	24776	1			T4	861		T60	1		T44	1
valid_sources[0x68]	24366	1			T4	746		T42	1		T52	2
valid_sources[0x69]	24464	1			T18	1		T4	707		T52	2
valid_sources[0x6a]	24224	1			T4	984		T10	1		T60	1
valid_sources[0x6b]	24740	1			T18	1		T4	198		T32	1
valid_sources[0x6c]	22743	1			T4	668		T15	1		T42	1
valid_sources[0x6d]	23576	1			T4	621		T10	3		T40	780
valid_sources[0x6e]	24374	1			T27	1		T4	729		T28	1
valid_sources[0x6f]	23671	1			T3	123		T27	1		T4	443
valid_sources[0x70]	24605	1			T27	1		T4	743		T44	5
valid_sources[0x71]	23070	1			T4	239		T10	3		T76	1
valid_sources[0x72]	23208	1			T4	1038		T44	1		T40	670
valid_sources[0x73]	25372	1			T4	334		T28	1		T50	1
valid_sources[0x74]	24423	1			T4	693		T10	1		T15	1
valid_sources[0x75]	23618	1			T4	578		T42	1		T52	2
valid_sources[0x76]	24885	1			T4	293		T51	5		T44	1
valid_sources[0x77]	25108	1			T4	872		T28	1		T32	1
valid_sources[0x78]	25173	1			T27	1		T4	578		T52	1
valid_sources[0x79]	25176	1			T4	522		T73	1		T40	809
valid_sources[0x7a]	24125	1			T19	3		T27	1		T4	762
valid_sources[0x7b]	25180	1			T19	3		T4	902		T42	2
valid_sources[0x7c]	25421	1			T4	283		T10	1		T44	1
valid_sources[0x7d]	24586	1			T18	2		T4	898		T60	1
valid_sources[0x7e]	25183	1			T4	555		T32	1		T60	1
valid_sources[0x7f]	23212	1			T4	555		T50	1		T52	2
valid_sources[0x80]	25358	1			T18	1		T4	338		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1399330

1

T1

5

T2

2

T18

14

values[0x0]

all_enables

biggest_size

2080104

1

T1

21

T2

33

T3

9

values[0x1]

all_enables

biggest_size

2075292

1

T1

17

T2

29

T3

22