Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2669	1			T2	2		T3	1		T4	60
non_zero_bins[1]	1671	1			T1	3		T2	5		T3	2
zero	8864	1			T1	1		T2	1		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	488	1			T3	1		T4	14		T42	1
uni	3499	1			T1	1		T2	1		T3	2
gen	4165	1			T1	1		T2	4		T3	2
res	798	1			T1	1		T2	2		T4	11
ins	4254	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8665

1

T1

3

T2

5

T3

4

mubi_true

4539

1

T1

1

T2

3

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

13

1

T90

1

T106

1

T258

1

pass

13191

1

T1

4

T2

8

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	123	1			T4	4		T40	4		T41	3
upd	non_zero_bins[0]	pass	mubi_true	119	1			T4	4		T42	1		T40	3
upd	non_zero_bins[1]	pass	mubi_false	75	1			T3	1		T4	3		T257	1
upd	non_zero_bins[1]	pass	mubi_true	73	1			T4	1		T40	3		T105	1
upd	zero	pass	mubi_false	43	1			T40	2		T41	2		T82	1
upd	zero	pass	mubi_true	55	1			T4	2		T40	2		T41	1
uni	zero	pass	mubi_false	2572	1			T1	1		T2	1		T3	2
uni	zero	pass	mubi_true	927	1			T4	15		T61	1		T52	1
gen	non_zero_bins[0]	pass	mubi_false	576	1			T4	13		T10	3		T44	3
gen	non_zero_bins[0]	pass	mubi_true	502	1			T4	11		T42	1		T11	3
gen	non_zero_bins[1]	pass	mubi_false	267	1			T1	1		T2	1		T4	2
gen	non_zero_bins[1]	pass	mubi_true	300	1			T2	3		T3	1		T4	2
gen	zero	fail	mubi_false	12	1			T90	1		T106	1		T258	1
gen	zero	pass	mubi_false	1777	1			T19	1		T27	1		T23	1
gen	zero	pass	mubi_true	731	1			T3	1		T18	2		T19	2
res	non_zero_bins[0]	pass	mubi_false	179	1			T2	2		T4	3		T24	3
res	non_zero_bins[0]	pass	mubi_true	183	1			T4	1		T52	1		T40	2
res	non_zero_bins[1]	pass	mubi_false	111	1			T4	1		T52	1		T105	2
res	non_zero_bins[1]	pass	mubi_true	128	1			T1	1		T4	1		T40	2
res	zero	fail	mubi_false	1	1			T291	1		-	-		-	-
res	zero	pass	mubi_false	117	1			T4	3		T10	2		T11	7
res	zero	pass	mubi_true	79	1			T4	2		T52	1		T40	2
ins	non_zero_bins[0]	pass	mubi_false	509	1			T3	1		T4	15		T11	1
ins	non_zero_bins[0]	pass	mubi_true	478	1			T4	9		T11	1		T61	1
ins	non_zero_bins[1]	pass	mubi_false	358	1			T1	1		T2	1		T4	3
ins	non_zero_bins[1]	pass	mubi_true	359	1			T4	7		T10	1		T61	1
ins	zero	pass	mubi_false	1945	1			T18	1		T19	1		T27	2
ins	zero	pass	mubi_true	605	1			T3	1		T18	1		T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded