Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
95.24 95.24 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_hw_cmd_sts_cg 95.24 1 100 1 64 64




Group Instance : edn_hw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.24 1 100 1 64 64




Summary for Group Instance edn_hw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 1 15 93.75
Crosses 5 0 5 100.00


Variables for Group Instance edn_hw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 4 0 4 100.00 100 1 1 0
cp_auto_mode 2 0 2 100.00 100 1 1 0
cp_boot_mode 2 0 2 100.00 100 1 1 0
cp_cmd_ack 2 0 2 100.00 100 1 1 0
cp_cmd_sts 6 1 5 83.33 100 1 1 0


Crosses for Group Instance edn_hw_cmd_sts_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_acmd_boot_mode 3 0 3 100.00 100 1 1 0
cr_acmd_auto_mode 2 0 2 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[UPD] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 63 1 T106 2 T76 1 T107 1
auto[RES] 18 1 T23 1 T150 1 T220 1
auto[GEN] 74 1 T1 1 T3 1 T107 1
auto[UNI] 7 1 T44 1 T193 1 T297 1



Summary for Variable cp_auto_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_auto_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_auto_mode 344 1 T1 1 T2 2 T3 1
auto_mode 56 1 T1 1 T3 1 T23 1



Summary for Variable cp_boot_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_boot_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_boot_mode 294 1 T1 2 T2 2 T3 2
boot_mode 106 1 T44 1 T106 2 T76 1



Summary for Variable cp_cmd_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 204 1 T1 1 T2 1 T3 1
ack 196 1 T1 1 T2 1 T3 1



Summary for Variable cp_cmd_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 1 5 83.33


Automatically Generated Bins for cp_cmd_sts

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 210 1 T1 1 T2 1 T3 1
auto[CMD_STS_INVALID_ACMD] 46 1 T1 1 T287 1 T298 1
auto[CMD_STS_INVALID_GEN_CMD] 50 1 T44 1 T107 1 T150 1
auto[CMD_STS_INVALID_CMD_SEQ] 45 1 T23 1 T106 1 T68 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 49 1 T2 1 T3 1 T17 1



Summary for Cross cr_acmd_boot_mode

Samples crossed: cp_acmd cp_boot_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
cp_acmdcp_boot_modeCOUNTSTATUS
[auto[INV]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[UPD]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_boot_mode , boot_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_boot_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] boot_mode 63 1 T106 2 T76 1 T107 1
auto[GEN] boot_mode 36 1 T107 1 T155 1 T96 1
auto[UNI] boot_mode 7 1 T44 1 T193 1 T297 1


User Defined Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_boot_mode 0 Excluded
not_valid_boot_commands 0 Excluded



Summary for Cross cr_acmd_auto_mode

Samples crossed: cp_acmd cp_auto_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
cp_acmdcp_auto_modeCOUNTSTATUS
[auto[INV]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[UPD]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_auto_mode , auto_mode] -- Excluded (4 bins)


Covered bins
cp_acmdcp_auto_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] auto_mode 18 1 T23 1 T150 1 T220 1
auto[GEN] auto_mode 38 1 T1 1 T3 1 T144 1


User Defined Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
not_auto_mode 0 Excluded
not_valid_boot_commands 0 Excluded

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